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ꢈ ꢊꢄꢋ ꢆꢌ ꢄꢍꢀ ꢊꢋꢁꢆ ꢎꢏ ꢐꢑꢅꢎ ꢌꢒꢊꢆ ꢓꢔ ꢎ ꢌꢕ ꢑꢆꢅ ꢖ
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SCBS077A − SEPTEMBER 1991 − REVISED NOVEMBER 1993
DW OR NT PACKAGE
(TOP VIEW)
• State-of-the-Art BiCMOS Design
Significantly Reduces I
CCZ
• ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
OE
1D
2D
3D
4D
5D
6D
7D
8D
V
CC
1
2
3
4
5
6
7
8
9
24
23 1Q
22 2Q
21 3Q
20 4Q
19 5Q
18 6Q
17 7Q
16 8Q
15 9Q
14 PRE
13 LE
• Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic 300-mil DIPs (NT)
description
The SN74BCT29844 features 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. It is particularly
suitable for implementing wider buffer registers,
I/O ports, bidirectional bus drivers with parity, and
working registers.
9D 10
CLR 11
GND 12
The nine latches are transparent D-type latches. When the latch-enable (LE) input is high, the Q outputs are
complementary to the inverting data (D) inputs.
A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high
or low level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
need for interface or pull-up components.
The output enable (OE) does not affect the internal operation of the flip-flops. Old data can be retained or new
data can be entered while the outputs are in the high-impedance state.
The SN74BCT29844 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUT
Q
PRE
L
CLR
X
OE
L
LE
X
D
X
X
L
H
L
H
L
L
X
H
H
L
H
H
L
H
L
H
H
L
H
X
X
H
H
L
Q
0
X
X
H
X
Z
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ꢚ
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ꢢ
ꢦ
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ꢤ
ꢞ
ꢞ
ꢥ
ꢥ
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ꢡ
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ꢟ
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ꢢ
ꢝ
ꢜ
ꢦ
ꢆꢥ
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ꢧ
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ꢨ
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ꢠ
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ꢝ
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ꢥ
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ꢪ
Copyright 1993, Texas Instruments Incorporated
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ꢡ ꢥ ꢢ ꢡꢚ ꢛꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ
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1
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