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SN74BCT29846NT-10

更新时间： 2024-11-14 15:52:11
品牌 Logo 应用领域
德州仪器 - TI 驱动信息通信管理光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
5页 90K
描述
BCT/FBT SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDIP24

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SN74BCT29846NT-10 技术参数

生命周期：Obsolete包装说明：DIP,
Reach Compliance Code：unknown风险等级：5.84
其他特性：WITH CLEAR AND PRESET; WITH TRIPLE OUTPUT ENABLE系列：BCT/FBT
JESD-30 代码：R-PDIP-T24长度：31.64 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
位数：8功能数量：1
端口数量：2端子数量：24
最高工作温度：70 °C最低工作温度：
输出特性：3-STATE输出极性：INVERTED
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
最大电源电流（ICC）：35 mA传播延迟（tpd）：10 ns
认证状态：Not Qualified座面最大高度：5.08 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：BICMOS温度等级：COMMERCIAL
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL宽度：7.62 mm
Base Number Matches：1

SN74BCT29846NT-10 数据手册

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SCBS023C − MARCH 1989 − REVISED APRIL 1994  
NT PACKAGE  
(TOP VIEW)  
• BiCMOS Process With CMOS Inputs and  
TTL Outputs Substantially Reduces  
Standby Current  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
OE1  
OE2  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
V
CC  
• Input Has 50-Ω Pullup Resister  
• Bus-Structured Pinout  
2
OE3  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
PRE  
LE  
3
• Functionally Equivalent to SN74ALS29846  
4
and AMD Am29846  
5
6
• Provides Extra Data Width Necessary For  
Wider Address/Data Paths or Buses With  
Parity  
7
8
9
• Power-Up High-Impedance State  
10  
11  
12  
8D  
CLR  
GND  
• Buffered Control Inputs to Reduce  
DC Loading Effects  
• Packaged in Standard Plastic 300-mil  
DIP (NT)  
description  
The SN74BCT29846 features 3-state outputs designed specifically for driving highly capacitive or relatively  
low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus  
drivers, and working registers.  
The eight latches of the SN74BCT29846 are transparent D-type latches. The SN74BCT29846 has inverting  
data (D) inputs. Since clear (CLR) and preset (PRE) are independent of the clock, taking the CLR input low will  
cause the eight Q outputs to go low. Taking the PRE input low will cause the eight Q outputs to go high. When  
both PRE and CLR are taken low, the outputs will follow the preset condition.  
The buffered output-enable (OE1, OE2, and OE3) inputs can be used to place the eight outputs in either a  
normal logic state (high or low levels) or a high-impedance state. The outputs are also in the high-impedance  
state during power-up and power-down conditions. The outputs remain in the high-impedance state while the  
device is powered-down. In the high-impedance state, the outputs neither load nor drive the bus lines  
significantly. The high-impedance state and increased drive provide the capability to drive the bus lines in a  
bus-organized system without need for interface or pull-up components. The output enables do not affect the  
internal operation of the latches. Old data can be retained or new data can be entered while the outputs are in  
the high-impedance state.  
The SN74BCT29846 is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Q
PRE  
L
CLR  
X
OE1  
L
OE2  
L
OE3  
L
LE  
X
D
X
X
L
H
L
H
L
L
L
L
X
H
H
L
L
L
H
H
L
H
L
H
H
L
L
L
H
X
X
X
X
H
H
L
L
L
Q
0
X
X
X
X
H
X
X
Z
X
X
X
H
X
X
Z
Z
X
X
H
X
X
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Copyright 1994, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
12345

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