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SN74BCT29853NT-10

更新时间： 2024-11-14 19:51:43
品牌 Logo 应用领域
德州仪器 - TI 信息通信管理光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
9页 212K
描述
BCT/FBT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDIP24

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SN74BCT29853NT-10 技术参数

生命周期：Obsolete包装说明：DIP,
Reach Compliance Code：unknown风险等级：5.76
其他特性：PARITY GENERATION A TO B; ERROR DETECTION B TO A; ODD PARITY系列：BCT/FBT
JESD-30 代码：R-PDIP-T24长度：31.64 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS TRANSCEIVER
位数：8功能数量：1
端口数量：2端子数量：24
最高工作温度：70 °C最低工作温度：
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
最大电源电流（ICC）：80 mA传播延迟（tpd）：10 ns
认证状态：Not Qualified座面最大高度：5.08 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：BICMOS温度等级：COMMERCIAL
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL宽度：7.62 mm
Base Number Matches：1

SN74BCT29853NT-10 数据手册

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SCBS002D − SEPTEMBER 1987 − REVISED APRIL 1994  
DW OR NT PACKAGE  
(TOP VIEW)  
• BiCMOS Process With TTL Inputs and  
Outputs  
• State-of-the-Art BiCMOS Design  
OEA  
A1  
V
CC  
B1  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
Significantly Reduces Standby Current  
2
• Flow-Through Pinout (All Inputs on  
A2  
B2  
3
Opposite Side From Outputs)  
A3  
B3  
4
A4  
B4  
5
• Functionally Equivalent to AMD Am29853  
A5  
B5  
6
• High-Speed Bus Transceiver With Parity  
A6  
B6  
7
Generator/Checker  
A7  
B7  
8
• Parity-Error Flag With Open-Collector  
A8  
B8  
9
Output  
ERR  
CLR  
PARITY  
OEB  
10  
11  
• Latch for Storage of the Parity-Error Flag  
• Package Options Include Plastic  
Small-Outline (DW) Packages and Standard  
Plastic 300-mil DIPs (NT)  
GND 12  
13 LE  
description  
The SN74BCT29853 is an 8-bit to 9-bit parity transceiver designed for asynchronous communication between  
data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted  
from the B to A bus with its corresponding parity bit, the parity-error (ERR) output will indicate whether or not  
an error in the B data has occurred. The output-enable (OEA, OEB) inputs can be used to disable the device  
so that the buses are effectively isolated.  
A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports  
with an open-collector parity-erro (ERR)r flag. ERR can be either passed, sampled, stored, or cleared from the  
latch using the latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is  
transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition  
which gives the designer more system diagnostic capability. The SN74BCT29853 provides true logic.  
The SN74BCT29853 is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
LE  
OUTPUT AND I/O  
†
Bi  
∑ of H’s  
FUNCTION  
Ai  
∑ of H’s  
‡
OEB  
L
OEA  
H
CLR  
X
A
NA  
B
B
A
PARITY  
ERR  
Odd  
Even  
L
H
X
L
NA  
NA  
A data to B bus and generate parity  
B data to A bus and check parity  
Odd  
Even  
H
L
H
L
X
NA  
NA  
NA  
H
X
L
H
L
H
H
NA  
X
X
X
X
X
NA  
NA  
NA  
NA  
N−1  
H
Store error flag  
X
Clear error-flag register  
H
L
X
X
H
H
L
X
X
NC  
H
H
§
H
L
H
L
X
Z
Z
A
Z
Isolation (parity check)  
L Odd  
H Even  
L
L
Odd  
Even  
H
L
A data to B bus and generate inverted  
parity  
X
X
NA  
NA  
NA  
NA = not applicable, NC = no change, X = don’t care  
†
‡
§
Summation of high-level inputs includes PARITY along with Bi inputs.  
Output states shown assume the ERR output was previously high.  
In this mode, the ERR output, when enabled, shows inverted parity of the A bus.  
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Copyright 1994, Texas Instruments Incorporated  
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2−1  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...9

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