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SN74BCT29841DW-00

更新时间： 2024-11-14 19:09:07
品牌 Logo 应用领域
德州仪器 - TI 驱动信息通信管理光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
5页 80K
描述
BCT/FBT SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24

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SN74BCT29841DW-00 技术参数

生命周期：Obsolete包装说明：SOP,
Reach Compliance Code：unknown风险等级：5.65
系列：BCT/FBTJESD-30 代码：R-PDSO-G24
长度：15.4 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER位数：10
功能数量：1端口数量：2
端子数量：24最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE最大电源电流（ICC）：35 mA
传播延迟（tpd）：10 ns认证状态：Not Qualified
座面最大高度：2.65 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：BICMOS
温度等级：COMMERCIAL端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
宽度：7.5 mmBase Number Matches：1

SN74BCT29841DW-00 数据手册

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SCBS024C − MARCH 1989 − REVISED NOVEMBER 1993  
SN54BCT29841 . . . JT OR W PACKAGE  
SN74BCT29841 . . . DW OR NT PACKAGE  
(TOP VIEW)  
• State-of-the-Art BiCMOS Design  
Significantly Reduces I  
CCZ  
• ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
24  
23 1Q  
22 2Q  
21 3Q  
20 4Q  
19 5Q  
18 6Q  
17 7Q  
16 8Q  
15 9Q  
14 10Q  
13 LE  
• Power-Up High-Impedance State  
• Provides Extra Bus-Driving Latches  
Necessary For Wider Address/Data Paths  
or Buses With Parity  
• Package Options Include Plastic  
Small-Outline (DW) Packages, Ceramic Chip  
Carriers (FK) and Flatpacks (W), and  
Standard Plastic and Ceramic 300-mil DIPs  
(JT, NT)  
9D 10  
10D 11  
GND 12  
description  
SN54BCT29841 . . . FK PACKAGE  
(TOP VIEW)  
These 10-bit bus-interface latches feature 3-state  
outputs designed specifically for driving highly  
capacitive or relatively low-impedance loads.  
They are particularly suitable for implementing  
wider buffer registers, I/O ports, bidirectional bus  
drivers with parity, and working registers.  
4
3
2
1
28 27 26  
25  
5
3D  
4D  
5D  
NC  
6D  
7D  
8D  
3Q  
4Q  
5Q  
6
24  
23  
The ten latches of the ′BCT29841 are transparent  
D-type latches. When the latch-enable (LE) input  
is high, the Q outputs will follow the data (D) inputs.  
When LE is taken low, the Q outputs are latched  
at the levels that were set up at the D inputs.  
7
8
22 NC  
21 6Q  
20 7Q  
19 8Q  
9
10  
11  
12 13 14 15 16 17 18  
A buffered output-enable (OE) input can be used  
to place the nine outputs in either a normal logic  
state (high or low level) or a high-impedance state.  
In the high-impedance state, the outputs neither  
load nor drive the bus lines significantly. The  
high-impedance state and increased drive provide  
the capability to drive bus lines without need for  
interface or pullup components.  
NC − No internal connection  
The output enable (OE) does not affect the internal operation of the latches. Old data can be retained or new  
data can be entered while the outputs are in the high-impedance state.  
The SN54BCT29841 is characterized for operation over the full military temperature range of −55°C to 125°C.  
The SN74BCT29841 is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Q
OE  
L
LE  
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
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Copyright 1993, Texas Instruments Incorporated  
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2−1  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
12345

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