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SN74BCT29843DWRE4 PDF预览

SN74BCT29843DWRE4

更新时间: 2024-11-14 15:52:11
品牌 Logo 应用领域
德州仪器 - TI 驱动信息通信管理光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
6页 141K
描述
BCT/FBT SERIES, 9-BIT DRIVER, TRUE OUTPUT, PDSO24, PLASTIC, SO-20

SN74BCT29843DWRE4 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:PLASTIC, SO-20针数:24
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.64Is Samacsys:N
其他特性:WITH CLEAR AND PRESET系列:BCT/FBT
JESD-30 代码:R-PDSO-G24长度:15.4 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.048 A位数:9
功能数量:1端口数量:2
端子数量:24最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP24,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):35 mA
Prop。Delay @ Nom-Sup:9 ns传播延迟(tpd):10 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:BICMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
Base Number Matches:1

SN74BCT29843DWRE4 数据手册

 浏览型号SN74BCT29843DWRE4的Datasheet PDF文件第2页浏览型号SN74BCT29843DWRE4的Datasheet PDF文件第3页浏览型号SN74BCT29843DWRE4的Datasheet PDF文件第4页浏览型号SN74BCT29843DWRE4的Datasheet PDF文件第5页浏览型号SN74BCT29843DWRE4的Datasheet PDF文件第6页 
ꢀꢁꢂ ꢃ ꢄ ꢅꢆ ꢇꢈ ꢉꢃꢊ  
ꢈ ꢋꢄꢌ ꢆꢍ ꢄꢎꢀ ꢋꢌꢁꢆ ꢏꢐ ꢑꢒꢅꢏ ꢍꢓꢋꢆ ꢔꢕ ꢏ ꢍꢖ ꢒꢆꢅ ꢗ  
ꢘ ꢌꢆ ꢗꢍ ꢊ ꢋꢀꢆꢒꢆ ꢏꢍ ꢙꢎ ꢆꢕ ꢎꢆ ꢀ  
SCBS022C − FEBRUARY 1989 − REVISED NOVEMBER 1993  
DW OR NT PACKAGE  
(TOP VIEW)  
BiCMOS Process With CMOS Inputs and  
TTL Outputs Substantially Reduces  
Standby Current  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
24  
Input Has 50 k  
23 1Q  
22 2Q  
21 3Q  
20 4Q  
19 5Q  
18 6Q  
17 7Q  
16 8Q  
15 9Q  
14 PRE  
13 LE  
Package Options Include Plastic  
Small-Outline (DW) Packages and Standard  
Plastic 300-mil DIPs (NT)  
description  
The SN74BCT29843 features 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. It is particularly  
suitable for implementing wider buffer registers,  
I/O ports, bidirectional bus drivers with parity, and  
working registers.  
9D 10  
CLR 11  
GND 12  
The nine latches are transparent D-type latches. When the latch-enable (LE) input is high, the Q outputs are  
complementary to the noninverting data (D) inputs.  
A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high  
or low level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus  
lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without  
need for interface or pull-up components.  
The output enable (OE) does not affect the internal operation of the flip-flops. Old data can be retained or new  
data can be entered while the outputs are in the high-impedance state.  
The SN74BCT29843 is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Q
PRE  
L
CLR  
X
OE  
L
LE  
X
D
X
X
L
H
L
H
L
L
X
H
H
L
H
H
L
L
H
H
L
H
X
X
H
H
H
L
Q
0
X
X
H
X
Z
ꢆꢥ  
Copyright 1993, Texas Instruments Incorporated  
ꢡ ꢥ ꢢ ꢡꢚ ꢛꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ  
ꢠꢞ  
2−1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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