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SN74BCT29834DW-00

更新时间： 2024-11-14 15:52:11
品牌 Logo 应用领域
德州仪器 - TI 信息通信管理光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
9页 212K
描述
BCT/FBT SERIES, 8-BIT TRANSCEIVER, INVERTED OUTPUT, PDSO24

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SN74BCT29834DW-00 技术参数

生命周期：Obsolete包装说明：SOP,
Reach Compliance Code：unknown风险等级：5.67
其他特性：INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; PARITY GENERATION A TO B; ERROR DETECTION B TO A系列：BCT/FBT
JESD-30 代码：R-PDSO-G24长度：15.4 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS TRANSCEIVER
位数：8功能数量：1
端口数量：2端子数量：24
最高工作温度：70 °C最低工作温度：
输出特性：3-STATE输出极性：INVERTED
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
最大电源电流（ICC）：80 mA传播延迟（tpd）：7 ns
认证状态：Not Qualified座面最大高度：2.65 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：BICMOS温度等级：COMMERCIAL
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL宽度：7.5 mm
Base Number Matches：1

SN74BCT29834DW-00 数据手册

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SCBS256 − SEPTEMBER 1987 − REVISED NOVEMBER 1993  
DW OR NT PACKAGE  
(TOP VIEW)  
• BiCMOS Process With TTL Inputs and  
Outputs  
• BiCMOS Design Reduces Standby Current  
OEA  
A1  
V
CC  
B1  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
• Flow-Through Pinout (All Inputs on  
2
Opposite Side From Outputs)  
A2  
B2  
3
A3  
B3  
4
• Functionally Equivalent to SN74ALS29834  
A4  
B4  
5
and AMD Am29834  
A5  
B5  
6
• High-Speed Bus Transceiver With Parity  
A6  
B6  
7
Generator/Checker  
A7  
B7  
8
• Parity-Error Flag With Open-Collector  
A8  
B8  
9
Output  
ERR  
CLR  
PARITY  
OEB  
10  
11  
• Available Register For Storage of the  
Parity-Error Flag  
GND 12  
13 CLK  
• Package Options Include Plastic  
Small-Outline (DW) Packages and Standard  
Plastic 300-mil DIPs (NT)  
description  
The SN74BCT29834 is an 8-bit to 9-bit parity transceiver designed for asynchronous communication between  
data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted  
from the B to A bus with its corresponding parity bit, the parity-error (ERR) output will indicate whether or not  
an error in the B data has occurred. The output-enable (OEA, OEB) inputs can be used to disable the device  
so that the buses are effectively isolated.  
A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports  
with an open-collector parity-error flag (ERR). ERR is clocked into the register on the rising edge of the CLK  
input. The error flag register is cleared with a low pulse on the clear (CLR) input. When both OEA and OEB are  
low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced  
error condition which gives the designer more system diagnostic capability. The SN74BCT29834 provides  
inverting logic.  
The SN74BCT29834 is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
CLK  
OUTPUT AND I/O  
†
Bi  
∑ of L’s  
FUNCTION  
Ai  
∑ of H’s  
‡
A
B
PARITY  
ERR  
OEB  
OEA  
CLR  
Odd  
Even  
H
L
L
H
X
X
NA  
NA  
A
NA  
A data to B bus and generate parity  
Odd  
Even  
H
L
H
X
L
H
L
↑
NA  
B
X
NA  
NA  
NA  
NA  
B data to A bus and check parity  
Clear error-flag register  
X
X
X
X
H
H
L
H
H
No↑  
No↑  
↑
X
X
Odd  
Even  
NC  
H
L
§
Isolation  
H
L
H
L
X
Z
Z
A
Z
↑
H
Odd  
Even  
L
H
A data to B bus and generate inverted  
parity  
X
X
NA  
NA  
NA  
NA = not applicable, NC = no change, X = don’t care  
†
‡
§
Summation of high-level inputs includes PARITY along with Bi inputs.  
Output states shown assume the ERR output was previously high.  
In this mode, the ERR output, when enabled, shows inverted parity of the A bus.  
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Copyright 1993, Texas Instruments Incorporated  
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2−1  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...9

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