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SN74AVC02PWR PDF预览

SN74AVC02PWR

更新时间： 2024-11-16 21:06:23
品牌 Logo 应用领域
德州仪器 - TI 输入元件光电二极管逻辑集成电路
页数 文件大小 规格书
9页 150K
描述
AVC SERIES, QUAD 2-INPUT NOR GATE, PDSO14, PLASTIC, TSSOP-14

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SN74AVC02PWR 技术参数

生命周期：Obsolete零件包装代码：TSSOP
包装说明：PLASTIC, TSSOP-14针数：14
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.84系列：AVC
JESD-30 代码：R-PDSO-G14长度：5 mm
逻辑集成电路类型：NOR GATE功能数量：4
输入次数：2端子数量：14
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP14,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.4 V标称供电电压 (Vsup)：1.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
宽度：4.4 mmBase Number Matches：1

SN74AVC02PWR 数据手册

 浏览型号SN74AVC02PWR的Datasheet PDF文件第2页浏览型号SN74AVC02PWR的Datasheet PDF文件第3页浏览型号SN74AVC02PWR的Datasheet PDF文件第4页浏览型号SN74AVC02PWR的Datasheet PDF文件第5页浏览型号SN74AVC02PWR的Datasheet PDF文件第6页浏览型号SN74AVC02PWR的Datasheet PDF文件第7页 
SN74AVC02  
QUADRUPLE 2-INPUT POSITIVE-NOR GATE  
SCES244C – APRIL 1999 – REVISED FEBRUARY 2000  
D
D
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
D
D
D
Overvoltage-Tolerant Inputs/Outputs Allow  
Mixed-Voltage-Mode Data Communications  
DOC (Dynamic Output Control) Circuit  
Dynamically Changes Output Impedance,  
Resulting in Noise Reduction Without  
Speed Degradation  
I
Supports Partial-Power-Down Mode  
off  
Operation  
Package Options Include Plastic  
Small-Outline (D), Thin Very Small-Outline  
(DGV), and Thin Shrink Small-Outline (PW)  
Packages  
D
Dynamic Drive Capability Is Equivalent to  
Standard Outputs With I  
and I  
of  
OH  
OL  
±24 mA at 2.5-V V  
CC  
description  
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output  
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1  
shows typical V vs I and V  
vs I  
curves to illustrate the output impedance and drive capability of the  
OL  
OL  
OH  
OH  
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is  
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC  
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC )  
Circuitry Technology and Applications, literature number SCEA009.  
3.2  
T
= 25°C  
T
= 25°C  
A
A
Process = Nominal  
Process = Nominal  
2.8  
2.4  
2.0  
2.8  
2.4  
2.0  
V
= 3.3 V  
CC  
1.6  
1.2  
0.8  
0.4  
1.6  
1.2  
0.8  
0.4  
V
= 2.5 V  
CC  
V
= 1.8 V  
CC  
V
= 3.3 V  
V
= 2.5 V  
CC  
CC  
V
= 1.8 V  
CC  
–160 –144 –128 –112 –96 –80 –64 –48 –32 –16  
– Output Current – mA  
0
17  
34  
51  
68  
85 102 119 136 153 170  
0
I
– Output Current – mA  
I
OH  
OL  
Figure 1. Output Voltage vs Output Current  
This quadruple 2-input positive-NOR gate is operational at 1.2-V to 3.6-V V , but is designed specifically for  
CC  
1.65-V to 3.6-V V  
operation.  
CC  
The SN74AVC02 performs the Boolean function Y = A + B or Y = A • B in positive logic.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
The SN74AVC02 is characterized for operation from –40°C to 85°C.  
DOC and EPIC are trademarks of Texas Instruments Incorporated.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
2–13  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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