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SN74AUP3G04_1 PDF预览

SN74AUP3G04_1

更新时间: 2024-11-16 06:12:55
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德州仪器 - TI /
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18页 809K
描述
LOW-POWER TRIPLE INVERTER GATE

SN74AUP3G04_1 数据手册

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SN74AUP3G04  
www.ti.com  
SCES762B DECEMBER 2009REVISED MARCH 2010  
LOW-POWER TRIPLE INVERTER GATE  
Check for Samples: SN74AUP3G04  
1
FEATURES  
Available in the Texas Instruments NanoStar™  
Package  
Optimized for 3.3-V Operation  
3.6-V I/O Tolerant to Support Mixed-Mode  
Signal Operation  
Low Static-Power Consumption  
(ICC = 0.9 mA Maximum)  
tpd = 4.3 ns Maximum at 3.3 V  
Low Dynamic-Power Consumption  
(Cpd = 4.3 pF Typ at 3.3 V)  
Suitable for Point-to-Point Applications  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Low Input Capacitance (Ci = 1.5 pF Typical)  
Low Noise – Overshoot and Undershoot  
<10% of VCC  
ESD Performance Tested Per JESD 22  
2000-V Human-Body Model  
(A114-B, Class II)  
Ioff Supports Partial-Power-Down Mode  
Operation  
1000-V Charged-Device Model (C101)  
Wide Operating VCC Range of 0.8 V to 3.6 V  
DCU PACKAGE  
(TOP VIEW)  
DQE PACKAGE  
(TOP VIEW)  
RSE PACKAGE  
(TOP VIEW)  
YFP PACKAGE  
(TOP VIEW)  
VCC  
8
7
6
5
VCC  
1
2
3
4
1A  
3Y  
A1  
B1  
C1  
D1  
A2 VCC  
VCC  
1 8  
2 7  
3 6  
4 5  
1
2
3
4
8
7
6
5
1A  
3Y  
1A  
3Y  
1Y  
3A  
2Y  
B2  
1Y  
1Y  
3A  
2Y  
8
1
2
3
7
6
5
1Y  
3A  
2Y  
1A  
3Y  
2A  
C2  
2A  
3A  
2A  
2A  
D2  
GND  
GND  
2Y  
GND  
4
GND  
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable  
applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range  
of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal  
integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).  
Static-Power Consumption  
(µA)  
Dynamic-Power Consumption  
(pF)  
Switching Characteristics  
at 25 MHz(A)  
100%  
80%  
60%  
40%  
20%  
0%  
100%  
80%  
60%  
40%  
20%  
0%  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
-0.5  
Input  
Output  
3.3-V  
Logic(A)  
3.3-V  
Logic(A)  
AUP  
AUP  
(A)  
20  
25  
Time (ns)  
10 15  
0
5
35 40 45  
30  
Single, dual, and triple gates  
(A) SN74AUP3Gxx data at C = 15 pF.  
L
Figure 1. AUP – The Lowest-Power Family  
Figure 2. Excellent Signal Integrity  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2009–2010, Texas Instruments Incorporated  
 

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