5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 栅极> SN74AUP3G34DQER
SN74AUP3G34DQER PDF预览

SN74AUP3G34DQER

更新时间： 2024-11-16 06:12:55
品牌 Logo 应用领域
德州仪器 - TI 栅极
页数 文件大小 规格书
12页 275K
描述
LOW-POWER TRIPLE BUFFER GATE

阅读下载

中文翻译

获取价格

SN74AUP3G34DQER 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SON
包装说明：VSON, SOLCC8,.04,14针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：1.65系列：AUP/ULP/V
JESD-30 代码：R-PDSO-N8JESD-609代码：e4
长度：1.4 mm负载电容（CL）：30 pF
逻辑集成电路类型：BUFFER最大I（ol）：0.004 A
湿度敏感等级：1功能数量：3
输入次数：1端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：VSON
封装等效代码：SOLCC8,.04,14封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, VERY THIN PROFILE包装方法：TR
峰值回流温度（摄氏度）：260电源：1.2/3.3 V
最大电源电流（ICC）：0.0009 mAProp。Delay @ Nom-Sup：25.5 ns
传播延迟（tpd）：25.5 ns认证状态：Not Qualified
施密特触发器：NO座面最大高度：0.4 mm
子类别：Gates最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：0.8 V标称供电电压 (Vsup)：1.2 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)
端子形式：NO LEAD端子节距：0.35 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：1 mmBase Number Matches：1

SN74AUP3G34DQER 数据手册

 浏览型号SN74AUP3G34DQER的Datasheet PDF文件第2页浏览型号SN74AUP3G34DQER的Datasheet PDF文件第3页浏览型号SN74AUP3G34DQER的Datasheet PDF文件第4页浏览型号SN74AUP3G34DQER的Datasheet PDF文件第5页浏览型号SN74AUP3G34DQER的Datasheet PDF文件第6页浏览型号SN74AUP3G34DQER的Datasheet PDF文件第7页 
SN74AUP3G34  
www.ti.com  
SCES766A –DECEMBER 2009–REVISED DECEMBER 2009  
LOW-POWER TRIPLE BUFFER GATE  
Check for Samples: SN74AUP3G34  
1
FEATURES  
•
•
•
Available in the Texas Instruments NanoStar™  
Package  
•
•
Optimized for 3.3-V Operation  
3.6-V I/O Tolerant to Support Mixed-Mode  
Signal Operation  
Low Static-Power Consumption  
(ICC = 0.9 μA Maximum)  
•
•
•
tpd = 4.3 ns Maximum at 3.3 V  
Low Dynamic-Power Consumption  
(Cpd = 4.3 pF Typ at 3.3 V)  
Suitable for Point-to-Point Applications  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
•
•
Low Input Capacitance (Ci = 1.5 pF Typical)  
Low Noise – Overshoot and Undershoot  
<10% of VCC  
•
ESD Performance Tested Per JESD 22  
–
2000-V Human-Body Model  
(A114-B, Class II)  
•
•
Ioff Supports Partial-Power-Down Mode  
Operation  
–
1000-V Charged-Device Model (C101)  
Wide Operating VCC Range of 0.8 V to 3.6 V  
DCU PACKAGE  
(TOP VIEW)  
DQE PACKAGE  
(TOP VIEW)  
RSE PACKAGE  
(TOP VIEW)  
YFP PACKAGE  
(TOP VIEW)  
VCC  
VCC  
1
2
3
4
8
7
6
5
1A  
3Y  
A1  
B1  
C1  
D1  
A2  
B2  
C2  
D2  
VCC  
1 8  
2 7  
3 6  
4 5  
VCC  
1Y  
3A  
2Y  
1
2
3
4
8
7
6
5
1A  
3Y  
1A  
3Y  
1Y  
3A  
2Y  
1Y  
3A  
2Y  
8
1
2
3
7
6
5
1Y  
3A  
2Y  
1A  
3Y  
2A  
2A  
2A  
2A  
GND  
GND  
GND  
4
GND  
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable  
applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range  
of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal  
integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).  
Static-Power Consumption  
(µA)  
Dynamic-Power Consumption  
(pF)  
Switching Characteristics  
at 25 MHz(A)  
100%  
80%  
60%  
40%  
20%  
0%  
100%  
80%  
60%  
40%  
20%  
0%  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
-0.5  
Input  
Output  
3.3-V  
Logic(A)  
3.3-V  
Logic(A)  
AUP  
AUP  
(A)  
20  
25  
Time (ns)  
10 15  
0
5
35 40 45  
30  
Single, dual, and triple gates  
(A) SN74AUP3Gxx data at C = 15 pF.  
L
Figure 1. AUP – The Lowest-Power Family  
Figure 2. Excellent Signal Integrity  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2009, Texas Instruments Incorporated  
 
1234567...12

中文翻译

下载PDF

SN74AUP3G34DQER 替代型号

型号 品牌 替代类型 描述 数据表
SN74AUP3G34DCURG4 TI

完全替代

 3 通道、0.8V 至 3.6V 低功耗缓冲器 | DCU | 8 | -40 to 85
SN74AUP3G34YFPR TI

完全替代

 LOW-POWER TRIPLE BUFFER GATE
SN74AUP3G34DCUR TI

完全替代

 LOW-POWER TRIPLE BUFFER GATE

与SN74AUP3G34DQER相关器件

型号 品牌 获取价格 描述 数据表
SN74AUP3G34RSER TI

获取价格

 		LOW-POWER TRIPLE BUFFER GATE
SN74AUP3G34YFPR TI

获取价格

 		LOW-POWER TRIPLE BUFFER GATE
SN74AVC TI

获取价格

 		16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SN74AVC02D TI

获取价格

 		AVC SERIES, QUAD 2-INPUT NOR GATE, PDSO14, PLASTIC, SO-14
SN74AVC02DGVR TI

获取价格

 		IC AVC SERIES, QUAD 2-INPUT NOR GATE, PDSO14, PLASTIC, TVSOP-14, Gate
SN74AVC02DR TI

获取价格

 		AVC SERIES, QUAD 2-INPUT NOR GATE, PDSO14, PLASTIC, SO-14
SN74AVC02PWR TI

获取价格

 		AVC SERIES, QUAD 2-INPUT NOR GATE, PDSO14, PLASTIC, TSSOP-14
SN74AVC04D TI

获取价格

 		AVC SERIES, HEX 1-INPUT INVERT GATE, PDSO14, PLASTIC, SO-14
SN74AVC04DGVR TI

获取价格

 		AVC SERIES, HEX 1-INPUT INVERT GATE, PDSO14, PLASTIC, TVSOP-14
SN74AVC04DR TI

获取价格

 		AVC SERIES, HEX 1-INPUT INVERT GATE, PDSO14, PLASTIC, SO-14

与SN74AUP3G34DQER相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证