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SN74AUP3G34RSER

更新时间： 2024-11-16 06:12:55
品牌 Logo 应用领域
德州仪器 - TI 栅极触发器逻辑集成电路
页数 文件大小 规格书
12页 275K
描述
LOW-POWER TRIPLE BUFFER GATE

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SN74AUP3G34RSER 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：QFN
包装说明：UQFN-8针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：1.66Is Samacsys：N
系列：AUP/ULP/VJESD-30 代码：S-PQCC-N8
JESD-609代码：e4长度：1.5 mm
负载电容（CL）：30 pF逻辑集成电路类型：BUFFER
最大I（ol）：0.004 A湿度敏感等级：1
功能数量：3输入次数：1
端子数量：8最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：VQCCN封装等效代码：LCC8,.06SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, VERY THIN PROFILE
包装方法：TR峰值回流温度（摄氏度）：260
电源：1.2/3.3 V最大电源电流（ICC）：0.0009 mA
Prop。Delay @ Nom-Sup：25.5 ns传播延迟（tpd）：25.5 ns
认证状态：Not Qualified施密特触发器：NO
座面最大高度：0.6 mm子类别：Gates
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：0.8 V
标称供电电压 (Vsup)：1.2 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：NICKEL PALLADIUM GOLD SILVER端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：1.5 mm
Base Number Matches：1

SN74AUP3G34RSER 数据手册

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SN74AUP3G34  
www.ti.com  
SCES766A –DECEMBER 2009–REVISED DECEMBER 2009  
LOW-POWER TRIPLE BUFFER GATE  
Check for Samples: SN74AUP3G34  
1
FEATURES  
•
•
•
Available in the Texas Instruments NanoStar™  
Package  
•
•
Optimized for 3.3-V Operation  
3.6-V I/O Tolerant to Support Mixed-Mode  
Signal Operation  
Low Static-Power Consumption  
(ICC = 0.9 μA Maximum)  
•
•
•
tpd = 4.3 ns Maximum at 3.3 V  
Low Dynamic-Power Consumption  
(Cpd = 4.3 pF Typ at 3.3 V)  
Suitable for Point-to-Point Applications  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
•
•
Low Input Capacitance (Ci = 1.5 pF Typical)  
Low Noise – Overshoot and Undershoot  
<10% of VCC  
•
ESD Performance Tested Per JESD 22  
–
2000-V Human-Body Model  
(A114-B, Class II)  
•
•
Ioff Supports Partial-Power-Down Mode  
Operation  
–
1000-V Charged-Device Model (C101)  
Wide Operating VCC Range of 0.8 V to 3.6 V  
DCU PACKAGE  
(TOP VIEW)  
DQE PACKAGE  
(TOP VIEW)  
RSE PACKAGE  
(TOP VIEW)  
YFP PACKAGE  
(TOP VIEW)  
VCC  
VCC  
1
2
3
4
8
7
6
5
1A  
3Y  
A1  
B1  
C1  
D1  
A2  
B2  
C2  
D2  
VCC  
1 8  
2 7  
3 6  
4 5  
VCC  
1Y  
3A  
2Y  
1
2
3
4
8
7
6
5
1A  
3Y  
1A  
3Y  
1Y  
3A  
2Y  
1Y  
3A  
2Y  
8
1
2
3
7
6
5
1Y  
3A  
2Y  
1A  
3Y  
2A  
2A  
2A  
2A  
GND  
GND  
GND  
4
GND  
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable  
applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range  
of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal  
integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).  
Static-Power Consumption  
(µA)  
Dynamic-Power Consumption  
(pF)  
Switching Characteristics  
at 25 MHz(A)  
100%  
80%  
60%  
40%  
20%  
0%  
100%  
80%  
60%  
40%  
20%  
0%  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
-0.5  
Input  
Output  
3.3-V  
Logic(A)  
3.3-V  
Logic(A)  
AUP  
AUP  
(A)  
20  
25  
Time (ns)  
10 15  
0
5
35 40 45  
30  
Single, dual, and triple gates  
(A) SN74AUP3Gxx data at C = 15 pF.  
L
Figure 1. AUP – The Lowest-Power Family  
Figure 2. Excellent Signal Integrity  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2009, Texas Instruments Incorporated  
 
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SN74AUP3G34RSER 替代型号

型号 品牌 替代类型 描述 数据表
SN74AUP3G34YFPR TI

完全替代

 LOW-POWER TRIPLE BUFFER GATE
SN74AUP3G34DQER TI

完全替代

 LOW-POWER TRIPLE BUFFER GATE
SN74AUP3G34DCUR TI

完全替代

 LOW-POWER TRIPLE BUFFER GATE

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