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SN74AUP2G17DCKR PDF预览

SN74AUP2G17DCKR

更新时间: 2024-11-16 11:58:23
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德州仪器 - TI /
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描述
LOW-POWER DUAL SCHMITT-TRIGGER BUFFER

SN74AUP2G17DCKR 数据手册

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SN74AUP2G17  
www.ti.com  
SCES750A SEPTEMBER 2009REVISED MAY 2010  
LOW-POWER DUAL SCHMITT-TRIGGER BUFFER  
Check for Samples: SN74AUP2G17  
1
FEATURES  
Available in the Texas Instruments NanoStar™  
Package  
Optimized for 3.3-V Operation  
3.6-V I/O Tolerant to Support Mixed-Mode  
Signal Operation  
Low Static-Power Consumption  
(ICC = 0.9 mA Maximum)  
tpd = 5.1 ns Maximum at 3.3 V  
Low Dynamic-Power Consumption  
(Cpd = 4.3 pF Typical at 3.3 V)  
Suitable for Point-to-Point Applications  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Low Input Capacitance (Ci = 1.5 pF Typical)  
Low Noise – Overshoot and Undershoot  
<10% of VCC  
ESD Performance Tested Per JESD 22  
2000-V Human-Body Model  
(A114-B, Class II)  
Ioff Supports Partial-Power-Down Mode  
Operation  
1000-V Charged-Device Model (C101)  
Wide Operating VCC Range of 0.8 V to 3.6 V  
DCK PACKAGE  
(TOP VIEW)  
DSF PACKAGE  
(TOP VIEW)  
YFP PACKAGE  
(TOP VIEW)  
DRY PACKAGE  
(TOP VIEW)  
A2  
A1  
B1  
1
2
6
5
4
1A  
GND  
2A  
1Y  
VCC  
2Y  
1
2
3
6
5
4
6
6
5
4
1
1A  
GND  
2A  
1
2
3
1A  
1Y  
1Y  
VCC  
2Y  
1A  
1Y  
B2  
C2  
5
4
2
3
VCC  
2Y  
GND  
2A  
C1 3  
VCC  
GND  
2A  
2Y  
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable  
applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range  
of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal  
integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).  
Static-Power Consumption  
Dynamic-Power Consumption  
Switching Characteristics  
at 25 MHz(A)  
(µA)  
(pF)  
100%  
80%  
60%  
40%  
20%  
0%  
100%  
3.5  
3.0  
80%  
60%  
40%  
20%  
0%  
2.5  
Input  
Output  
2.0  
3.3-V  
Logic(A)  
3.3-V  
Logic(A)  
1.5  
1.0  
0.5  
AUP  
AUP  
0.0  
−0.5  
(A)  
20  
25  
Time (ns)  
10 15  
0
5
35 40 45  
30  
Single, dual, and triple gates  
(A) SN74AUP2Gxx data at C = 15 pF.  
L
Figure 1. AUP – The Lowest-Power Family  
Figure 2. Excellent Signal Integrity  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
UNLESS OTHERWISE NOTED this document contains  
PRODUCTION DATA information current as of publication date.  
Products conform to specifications per the terms of Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2009–2010, Texas Instruments Incorporated  
 

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