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SN74AUP2G79DCUR

更新时间： 2024-11-16 11:51:35
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德州仪器 - TI 触发器
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14页 283K
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LOW-POWER DUAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP

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SN74AUP2G79DCUR 数据手册

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SN74AUP2G79  
www.ti.com  
SCES755A –DECEMBER 2009–REVISED DECEMBER 2009  
LOW-POWER DUAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP  
Check for Samples: SN74AUP2G79  
1
FEATURES  
•
•
•
Available in the Texas Instruments NanoStar™  
Package  
•
•
Optimized for 3.3-V Operation  
3.6-V I/O Tolerant to Support Mixed-Mode  
Signal Operation  
Low Static-Power Consumption  
(ICC = 0.9 μA Maximum)  
•
•
•
tpd = 4 ns Maximum at 3.3 V  
Low Dynamic-Power Consumption  
(Cpd = 3 pF Typ at 3.3 V)  
Suitable for Point-to-Point Applications  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
•
•
Low Input Capacitance (Ci = 1.5 pF Typical)  
Low Noise – Overshoot and Undershoot  
<10% of VCC  
•
ESD Performance Tested Per JESD 22  
–
2000-V Human-Body Model  
(A114-B, Class II)  
•
•
Ioff Supports Partial-Power-Down Mode  
Operation  
–
1000-V Charged-Device Model (C101)  
Wide Operating VCC Range of 0.8 V to 3.6 V  
DCU PACKAGE  
(TOP VIEW)  
DQE PACKAGE  
(TOP VIEW)  
RSE PACKAGE  
(TOP VIEW)  
YFP PACKAGE  
(TOP VIEW)  
VCC  
VCC  
A1  
B1  
C1  
D1  
A2  
B2  
C2  
D2  
1
2
3
4
8
7
6
5
1 8  
2 7  
3 6  
4 5  
VCC  
1CLK  
1D  
VCC  
1CLK  
1D  
2Q  
1
2
3
4
8
7
6
5
1CLK  
1D  
1Q  
2D  
1Q  
2D  
1Q  
8
1
2
3
7
6
5
1Q  
2D  
1CLK  
1D  
2Q  
2Q  
2D  
GND  
2CLK  
GND  
2CLK  
GND  
2CLK  
2CLK  
2Q  
4
GND  
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable  
applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range  
of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal  
integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).  
Static-Power Consumption  
(µA)  
Dynamic-Power Consumption  
(pF)  
Switching Characteristics  
at 25 MHz(A)  
100%  
80%  
60%  
40%  
20%  
0%  
100%  
80%  
60%  
40%  
20%  
0%  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
-0.5  
Input  
Output  
3.3-V  
Logic(A)  
3.3-V  
Logic(A)  
AUP  
AUP  
(A)  
20  
25  
Time (ns)  
10 15  
0
5
35 40 45  
30  
Single, dual, and triple gates  
(A) SN74AUP2Gxx data at C = 15 pF.  
L
Figure 1. AUP – The Lowest-Power Family  
Figure 2. Excellent Signal Integrity  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2009, Texas Instruments Incorporated  
 
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SN74AUP2G79DCUR 替代型号

型号 品牌 替代类型 描述 数据表
SN74AUP2G79DQER TI

完全替代

 LOW-POWER DUAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP
SN74AUP2G79YFPR TI

完全替代

 LOW-POWER DUAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP
SN74AUP2G79RSER TI

功能相似

 LOW-POWER DUAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP

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