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SN74AUP2G34

更新时间： 2024-09-28 11:58:23

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
19页	907K
描述
LOW-POWER DUAL BUFFER GATE

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SN74AUP2G34 数据手册

SN74AUP2G34

www.ti.com

SCES751B –SEPTEMBER 2009–REVISED MARCH 2010

LOW-POWER DUAL BUFFER GATE

Check for Samples: SN74AUP2G34

FEATURES

•

Available in the Texas Instruments NanoStar™

Package

•

Optimized for 3.3-V Operation

3.6-V I/O Tolerant to Support Mixed-Mode

Signal Operation

Low Static-Power Consumption:

I_CC= 0.9 mA Max

•

t_pd= 4.3 ns Max at 3.3 V

Low Dynamic-Power Consumption:

C_pd= 4.3 pF Typ at 3.3 V

Suitable for Point-to-Point Applications

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

•

Low Input Capacitance: C_i= 1.5 pF Typ

Low Noise: Overshoot and Undershoot

<10% of V_CC

•

ESD Performance Tested Per JESD 22

–

2000-V Human-Body Model

(A114-B, Class II)

•

I_offSupports Partial-Power-Down Mode

Operation

–

1000-V Charged-Device Model (C101)

Wide Operating V_CCRange of 0.8 V to 3.6 V

DCK PACKAGE

(TOP VIEW)

DSF PACKAGE

(TOP VIEW)

YFP PACKAGE

(TOP VIEW)

DRY PACKAGE

(TOP VIEW)

GND

V_CC

GND

V_CC

GND

C1 3

V_CC

GND

See mechanical drawings for dimensions.

DESCRIPTION/ORDERING INFORMATION

The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable

applications. This family ensures a very low static- and dynamic-power consumption across the entire V_CCrange

of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal

integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).

Switching Characteristics

Static-Power Consumption

Dynamic-Power Consumption

at 25 MHz^(A)

(µA)

(pF)

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

-0.5

100%

80%

60%

40%

20%

100%

80%

60%

40%

20%

Input

Output

3.3-V

Logic^(A)

3.3-V

Logic^(A)

AUP

Time (ns)

10 15

35 40 45

(A)

Single, dual, and triple gates

^(A)SN74AUP2Gxx data at C = 15 pF.

Figure 1. AUP – The Lowest-Power Family

Figure 2. Excellent Signal Integrity

The SN74AUP2G34 performs the Boolean function Y = A in positive logic.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the

package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...19

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与SN74AUP2G34相关器件

型号	品牌	获取价格	描述	数据表
SN74AUP2G34DCKR	TI	获取价格	LOW-POWER DUAL BUFFER GATE
SN74AUP2G34DRYR	TI	获取价格	LOW-POWER DUAL BUFFER GATE
SN74AUP2G34DSFR	TI	获取价格	LOW-POWER DUAL BUFFER GATE
SN74AUP2G34YFPR	TI	获取价格	LOW-POWER DUAL BUFFER GATE
SN74AUP2G79	TI	获取价格	LOW-POWER DUAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP
SN74AUP2G79DCUR	TI	获取价格	LOW-POWER DUAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP
SN74AUP2G79DQER	TI	获取价格	LOW-POWER DUAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP
SN74AUP2G79RSER	TI	获取价格	LOW-POWER DUAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP
SN74AUP2G79YFPR	TI	获取价格	LOW-POWER DUAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP
SN74AUP2G80	TI	获取价格	LOW-POWER DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

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