Datasheet > SN74AUP1G125_101

SN74AUP1G125_101

更新时间： 2024-01-22 08:27:29

品牌	Logo	应用领域
德州仪器 - TI		输出元件
页数	文件大小	规格书
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LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT

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SN74AUP1G125_101 数据手册

SN74AUP1G125

www.ti.com

SCES595J –JULY 2004–REVISED MARCH 2010

LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT

Check for Samples: SN74AUP1G125

FEATURES

•

Available in the Texas Instruments NanoStar™

Package

•

Wide Operating V_CCRange of 0.8 V to 3.6 V

Optimized for 3.3-V Operation

Low Static-Power Consumption

(I_CC= 0.9 mA Max)

3.6-V I/O Tolerant to Support Mixed-Mode

Signal Operation

Low Dynamic-Power Consumption

(C_pd= 4 pF Typ at 3.3 V)

•

t_pd= 4.6 ns Max at 3.3 V

Suitable for Point-to-Point Applications

•

Low Input Capacitance (C_I= 1.5 pF Typ)

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

Low Noise – Overshoot and Undershoot

<10% of V_CC

•

ESD Performance Tested Per JESD 22

•

Input-Disable Feature Allows Floating Input

Conditions

–

2000-V Human-Body Model

(A114-B, Class II)

I_offSupports Partial-Power-Down Mode

Operation

–

1000-V Charged-Device Model (C101)

Input Hysteresis Allows Slow Input Transition

and Better Switching Noise Immunity at Input

DBV PACKAGE

(TOP VIEW)

DCK PACKAGE

(TOP VIEW)

DRL PACKAGE

(TOP VIEW)

V_CC

GND

DSF PACKAGE

(TOP VIEW)

YFP PACKAGE

(TOP VIEW)

YZP PACKAGE

(TOP VIEW)

DRY PACKAGE

(TOP VIEW)

V_CC

N.C.

DNU

N.C.

C1 3

GND

N.C. – No internal connection.

DNU – Do not use

See mechancial drawings for dimensions.

DESCRIPTION/ORDERING INFORMATION

The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable

applications. This family ensures a very low static and dynamic power consumption across the entire V_CCrange

of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see

Figure 1 and Figure 2).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...24

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与SN74AUP1G125_101相关器件

型号	品牌	获取价格	描述	数据表
SN74AUP1G125DBVR	TI	获取价格	LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
SN74AUP1G125DBVT	TI	获取价格	LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
SN74AUP1G125DCK	TI	获取价格	AUP/ULP/V SERIES, 1-BIT DRIVER, TRUE OUTPUT, PDSO5
SN74AUP1G125DCKR	TI	获取价格	LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
SN74AUP1G125DCKT	TI	获取价格	LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
SN74AUP1G125DPWR	TI	获取价格	具有三态输出的单路 0.8V 至 3.6V 低功耗缓冲器 \| DPW \| 5 \| -40
SN74AUP1G125DRLR	TI	获取价格	LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
SN74AUP1G125DRYR	TI	获取价格	LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
SN74AUP1G125DSFR	TI	获取价格	LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
SN74AUP1G125YEPR	TI	获取价格	LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT

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