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SN74AUP1G125DCK PDF预览

SN74AUP1G125DCK

更新时间： 2024-02-02 18:08:19
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
29页 1337K
描述
AUP/ULP/V SERIES, 1-BIT DRIVER, TRUE OUTPUT, PDSO5

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SN74AUP1G125DCK 技术参数

生命周期：Obsolete包装说明：TSSOP, TSSOP5/6,.08
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.62系列：AUP/ULP/V
JESD-30 代码：R-PDSO-G5长度：2 mm
逻辑集成电路类型：BUS DRIVER位数：1
功能数量：1端口数量：2
端子数量：5最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP5/6,.08
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟（tpd）：21.4 ns座面最大高度：1.1 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：0.8 V
标称供电电压 (Vsup)：1.2 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL宽度：1.25 mm
Base Number Matches：1

SN74AUP1G125DCK 数据手册

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SN74AUP1G125  
www.ti.com  
SCES595L –JULY 2004–REVISED FEBRUARY 2013  
LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT  
Check for Samples: SN74AUP1G125  
1
FEATURES  
2
•
•
•
Available in the Texas Instruments NanoStar™  
Package  
•
•
•
Wide Operating VCC Range of 0.8 V to 3.6 V  
Optimized for 3.3-V Operation  
Low Static-Power Consumption  
(ICC = 0.9 μA Max)  
3.6-V I/O Tolerant to Support Mixed-Mode  
Signal Operation  
Low Dynamic-Power Consumption  
(Cpd = 4 pF Typ at 3.3 V)  
•
•
•
tpd = 4.6 ns Max at 3.3 V  
Suitable for Point-to-Point Applications  
•
•
Low Input Capacitance (CI = 1.5 pF Typ)  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Low Noise – Overshoot and Undershoot  
<10% of VCC  
•
ESD Performance Tested Per JESD 22  
•
•
•
Input-Disable Feature Allows Floating Input  
Conditions  
–
2000-V Human-Body Model  
(A114-B, Class II)  
Ioff Supports Partial-Power-Down Mode  
Operation  
–
1000-V Charged-Device Model (C101)  
Input Hysteresis Allows Slow Input Transition  
and Better Switching Noise Immunity at Input  
DBV PACKAGE  
(TOP VIEW)  
DCK PACKAGE  
(TOP VIEW)  
DRL PACKAGE  
(TOP VIEW)  
5
OE  
VCC  
1
2
3
VCC  
1
2
3
5
OE  
A
1
2
3
5
VCC  
OE  
A
A
4
Y
GND  
4
GND  
Y
4
Y
GND  
DSF P CKAGE  
A
(TOP VIEW)  
YFP PACKAGE  
(TOP VIEW)  
YZP/YZT PACKAGE  
(TOP VIEW)  
DRY PACKAGE  
(TOP VIEW)  
6
5
4
1
2
3
A1  
B1  
C1  
1
2
3
6 A2  
5 B2  
A1  
B1  
C1  
1
2
3
5 A2  
V
VCC  
OE  
A
VCC  
Y
OE  
A
OE  
A
6
5
4
1
2
3
CC  
VCC  
N.C.  
Y
OE  
DNU  
Y
N.C.  
Y
A
4
4 C2  
C2  
GND  
GND  
GND  
GND  
N.C. – No internal connection.  
DNU – Do not use  
See mechancial drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable  
applications. This family ensures a very low static and dynamic power consumption across the entire VCC range  
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see  
Figure 1 and Figure 2).  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
NanoStar is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2004–2013, Texas Instruments Incorporated  
 
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