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SN74AUP1G125DPWR PDF预览

SN74AUP1G125DPWR

更新时间： 2023-06-19 15:34:52
品牌 Logo 应用领域
德州仪器 - TI 驱动逻辑集成电路
页数 文件大小 规格书
15页 299K
描述
具有三态输出的单路 0.8V 至 3.6V 低功耗缓冲器 | DPW | 5 | -40 to 85

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SN74AUP1G125DPWR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：VBCC,
Reach Compliance Code：compliantECCN代码：EAR99
Factory Lead Time：8 weeks风险等级：1.28
系列：AUP/ULP/VJESD-30 代码：S-PBCC-B5
JESD-609代码：e4长度：0.8 mm
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.004 A
湿度敏感等级：1位数：1
功能数量：1端口数量：2
端子数量：5最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：VBCC封装形状：SQUARE
封装形式：CHIP CARRIER, VERY THIN PROFILE峰值回流温度（摄氏度）：NOT SPECIFIED
最大电源电流（ICC）：0.0009 mA传播延迟（tpd）：21.4 ns
座面最大高度：0.4 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：0.8 V标称供电电压 (Vsup)：1.2 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：BUTT端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：0.8 mm

SN74AUP1G125DPWR 数据手册

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SN74AUP1G125  
LOW-POWER SINGLE BUS BUFFER GATE  
WITH 3-STATE OUTPUT  
www.ti.com  
SCES595E–JULY 2004–REVISED JULY 2005  
FEATURES  
•
•
•
Available in the Texas Instruments  
NanoStar™ and NanoFree™ Packages  
•
•
•
Wide Operating VCC Range of 0.8 V to 3.6 V  
Optimized for 3.3-V Operation  
Low Static-Power Consumption  
(ICC = 0.0 µA Max)  
3.6-V I/O Tolerant to Support Mixed-Mode  
Signal Operation  
Low Dynamic-Power Consumption  
(Cpd = 4 pF Typ at 3.3 V)  
•
•
•
tpd = 4.6 ns Max at 3.3 V  
Suitable for Point-to-Point Applications  
•
•
Low Input Capacitance (Ci = 1.5 pF Typ)  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Low Noise – Overshoot and Undershoot  
<10% of VCC  
•
ESD Performance Tested Per JESD 22  
•
•
•
Input-Disable Feature Allows Floating Input  
Conditions  
– 2000-V Humna-Body Model  
(A114-B, Class II)  
Ioff Supports Partial-Power-Down Mode  
Operation  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
Input Hysteresis Allows Slow Input Transition  
and Better Switching Noise Immunity at Input  
•
ESD Protection Exceeds ±5000 V With  
Human-Body Model  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
DBV PACKAGE  
(TOP VIEW)  
DCK PACKAGE  
(TOP VIEW)  
DRL PACKAGE  
(TOP VIEW)  
3
4
Y
GND  
A
1
2
3
5
OE  
A
V
CC  
OE  
A
V
1
2
3
5
CC  
1
2
3
5
4
OE  
A
V
Y
CC  
2
1
5
V
OE  
CC  
4
GND  
Y
4
GND  
Y
GND  
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable  
applications. This family ensures a very low static and dynamic power consumption across the entire VCC range  
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see  
Figures 1 and 2).  
xxxx  
Switching Characteristics  
†
Static-Power Consumption  
Dynamic-Power Consumption  
(pF)  
at 25 MHz  
(µA)  
3.5  
3
100%  
80%  
100%  
2.5  
2
80%  
Input  
Output  
1.5  
1
60%  
40%  
60%  
40%  
3.3-V  
3.3-V  
†  
†
Logic  
Logic  
0.5  
0
20%  
0%  
20%  
0%  
−0.5  
20  
Time − ns  
AUP  
0
5
10  
15  
25  
35 40 45  
AUP  
30  
†
Single, dual, and triple gates  
†
AUP1G08 data at C = 15 pF  
L
Figure 1. AUP – The Lowest-Power Family  
Figure 2. Excellent Signal Integrity  
xxx  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar, NanoFree are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2004–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...15

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