5秒后页面跳转
捷配首页

Datasheet > SN74AUP1G126DBVRE4
SN74AUP1G126DBVRE4 PDF预览

SN74AUP1G126DBVRE4

更新时间： 2024-11-26 14:38:35
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
15页 233K
描述
IC,BUFFER/DRIVER,SINGLE,1-BIT,CMOS,TSOP,5PIN,PLASTIC

阅读下载

中文翻译

获取价格

SN74AUP1G126DBVRE4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete包装说明：LSSOP, TSOP5/6,.11,37
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.63控制类型：ENABLE HIGH
系列：AUP/ULP/VJESD-30 代码：R-PDSO-G5
长度：2.9 mm负载电容（CL）：30 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.0017 A
位数：1功能数量：1
端口数量：2端子数量：5
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：LSSOP
封装等效代码：TSOP5/6,.11,37封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, LOW PROFILE, SHRINK PITCH包装方法：TR
峰值回流温度（摄氏度）：NOT SPECIFIED电源：1.2/3.3 V
Prop。Delay @ Nom-Sup：21.4 ns传播延迟（tpd）：21.4 ns
认证状态：Not Qualified座面最大高度：1.45 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：0.8 V标称供电电压 (Vsup)：1.2 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.95 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：1.6 mm
Base Number Matches：1

SN74AUP1G126DBVRE4 数据手册

 浏览型号SN74AUP1G126DBVRE4的Datasheet PDF文件第2页浏览型号SN74AUP1G126DBVRE4的Datasheet PDF文件第3页浏览型号SN74AUP1G126DBVRE4的Datasheet PDF文件第4页浏览型号SN74AUP1G126DBVRE4的Datasheet PDF文件第5页浏览型号SN74AUP1G126DBVRE4的Datasheet PDF文件第6页浏览型号SN74AUP1G126DBVRE4的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢇꢉ ꢊ  
ꢋ ꢌꢍꢎꢆꢌ ꢍ ꢏꢐ ꢀꢑ ꢁꢈ ꢋ ꢏ ꢒꢅꢀ ꢒꢅꢓ ꢓ ꢏ ꢐ ꢈ ꢄꢔꢏ  
ꢍ ꢑꢔ ꢕ ꢖ ꢎꢀꢔꢄꢔ ꢏ ꢌ ꢅꢔ ꢆ ꢅꢔ  
SCES596B – JULY 2004 – REVISED APRIL 2005  
D
D
D
Available in the Texas Instruments  
NanoStarand NanoFreePackages  
Low Static-Power Consumption  
D
Wide Operating V  
Range of 0.8 V to 3.6 V  
CC  
D
Optimized for 3.3-V Operation  
D
D
D
D
3.6-V I/O Tolerant to Support Mixed-Mode  
Signal Operation  
(I  
= 0.9 µA Max)  
CC  
Low Dynamic-Power Consumption  
t
= 4.6 ns Max at 3.3 V  
pd  
(C = 4 pF Typ at 3.3 V)  
pd  
Suitable for Point-to-Point Applications  
D
Low Input Capacitance (C = 1.5 pF Typ)  
i
Low Noise − Overshoot and Undershoot  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
D
<10% of V  
CC  
D
ESD Performance Tested Per JESD 22  
− 2000-V Human-Body Model  
(A114-B, Class II)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
D
D
D
Input-Disable Feature Allows Floating Input  
Conditions  
I
Supports Partial-Power-Down Mode  
off  
Operation  
Input Hysteresis Allows Slow Input  
Transition and Better Switching Noise  
Immunity at Input  
D
ESD Protection Exceeds 5000 V With  
Human-Body Model  
DBV, DCK, OR DRL PACKAGE  
(TOP VIEW)  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
3 4  
2
GND  
A
OE  
Y
V
1
2
3
5
4
OE  
A
GND  
V
Y
CC  
1 5  
CC  
description/ordering information  
The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable  
applications. This family ensures a very low static and dynamic power consumption across the entire V range  
CC  
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see  
Figures 1 and 2).  
Static-Power Consumption  
Dynamic-Power Consumption  
(pF)  
Switching Characteristics  
†
(µA)  
at 25 MHz  
3.5  
3
100%  
100%  
80%  
60%  
80%  
2.5  
2
Input  
Output  
60%  
40%  
3.3-V  
3.3-V  
†  
Logic  
1.5  
1
†
Logic  
40%  
0.5  
0
20%  
0%  
20%  
0%  
AUP  
AUP  
−0.5  
10  
15 20  
Time − ns  
0
5
25  
35 40 45  
30  
†
Single, dual, and triple gates  
†
AUP1G08 data at C = 15 pF  
L
Figure 2. Excellent Signal Integrity  
Figure 1. AUP − The Lowest-Power Family  
This bus buffer gate is a single line driver with a 3-state output. The output is disabled when the output-enable  
(OE) input is low. This device has the input-disable feature, which allows floating input signals.  
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a  
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the  
driver.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar and NanoFree are trademarks of Texas Instruments.  
ꢆ
ꢆ
ꢐ
ꢌ
ꢨ
ꢗ
ꢣ
ꢅ
ꢘ
ꢡ
ꢔ
ꢢ
ꢑ
ꢜ
ꢌ
ꢚ
ꢁ
ꢛ
ꢗ
ꢄ
ꢔ
ꢄ
ꢙ
ꢚ
ꢤ
ꢛ
ꢜ
ꢢ
ꢝ
ꢞ
ꢟ
ꢟ
ꢠ
ꢠ
ꢙ
ꢙ
ꢜ
ꢜ
ꢚ
ꢚ
ꢙ
ꢡ
ꢡ
ꢥ
ꢢ
ꢣ
ꢝ
ꢝ
ꢤ
ꢤ
ꢚ
ꢠ
ꢟ
ꢞ
ꢡ
ꢡ
ꢜ
ꢛ
ꢥ
ꢔꢤ  
ꢣ
ꢦ
ꢡ
ꢧ
ꢙ
ꢢ
ꢟ
ꢡ
ꢠ
ꢙ
ꢠ
ꢜ
ꢝ
ꢚ
ꢣ
ꢨ
ꢟ
ꢚ
ꢠ
ꢠ
ꢤ
ꢡ
ꢩ
Copyright 2005, Texas Instruments Incorporated  
ꢝ
ꢜ
ꢢ
ꢠ
ꢜ
ꢝ
ꢞ
ꢠ
ꢜ
ꢡ
ꢥ
ꢙ
ꢛ
ꢙ
ꢢ
ꢤ
ꢝ
ꢠ
ꢪ
ꢠ
ꢤ
ꢝ
ꢜ
ꢛ
ꢫ
ꢟ
ꢑ
ꢚ
ꢞ
ꢤ
ꢡ
ꢠ
ꢟ
ꢚ
ꢨ
ꢟ
ꢝ
ꢨ
ꢬ
ꢟ
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
ꢝ
ꢝ
ꢟ
ꢚ
ꢠ
ꢭ
ꢩ
ꢆ
ꢝ
ꢜ
ꢨ
ꢣ
ꢢ
ꢠ
ꢙ
ꢜ
ꢚ
ꢥ
ꢝ
ꢜ
ꢢ
ꢤ
ꢡ
ꢡ
ꢙ
ꢚ
ꢮ
ꢨ
ꢜ
ꢤ
ꢡ
ꢚ
ꢜ
ꢠ
ꢚ
ꢤ
ꢢ
ꢤ
ꢡ
ꢡ
ꢟ
ꢝ
ꢙ
ꢧ
ꢭ
ꢙ
ꢚ
ꢢ
ꢧ
ꢣ
ꢨ
ꢤ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...15

中文翻译

下载PDF

与SN74AUP1G126DBVRE4相关器件

型号 品牌 获取价格 描述 数据表
SN74AUP1G126DBVT TI

获取价格

 		LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
SN74AUP1G126DBVTE4 TI

获取价格

 		IC,BUFFER/DRIVER,SINGLE,1-BIT,CMOS,TSOP,5PIN,PLASTIC
SN74AUP1G126DCKR TI

获取价格

 		LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATS OUTPUT
SN74AUP1G126DCKR UMW

获取价格

 		逻辑集成电路
SN74AUP1G126DCKRE4 TI

获取价格

 		IC,BUFFER/DRIVER,SINGLE,1-BIT,CMOS,TSSOP,5PIN,PLASTIC
SN74AUP1G126DCKT TI

获取价格

 		LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
SN74AUP1G126DCKTE4 TI

获取价格

 		IC IC,BUFFER/DRIVER,SINGLE,1-BIT,CMOS,TSSOP,5PIN,PLASTIC, Bus Driver/Transceiver
SN74AUP1G126DPWR TI

获取价格

 		具有三态输出的单路 0.8V 至 3.6V 低功耗缓冲器 | DPW | 5 | -40
SN74AUP1G126DRLR TI

获取价格

 		LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATS OUTPUT
SN74AUP1G126DRYR TI

获取价格

 		LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT

与SN74AUP1G126DBVRE4相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证