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SN74AUP1G08DPWR

更新时间： 2024-02-26 00:03:06
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德州仪器 - TI 输入元件
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SCES502B − NOVEMBER 2003 − REVISED AUGUST 2004  
D
D
D
Available in the Texas Instruments  
NanoStarand NanoFreePackages  
Low Static-Power Consumption;  
D
D
D
D
D
D
Wide Operating V  
Range of 0.8 V to 3.6 V  
CC  
Optimized for 3.3-V Operation  
3.6-V I/O Tolerant to Support Mixed-Mode  
Signal Operation  
I
= 0.9 µA Max  
CC  
Low Dynamic-Power Consumption;  
= 4.3 pF Typ at 3.3 V  
t
= 4.3 ns Max at 3.3 V  
pd  
C
pd  
Suitable for Point-to-Point Applications  
D
Low Input Capacitance; C = 1.5 pF Typ  
i
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
D
Low Noise − Overshoot and Undershoot  
<10% of V  
CC  
D
ESD Performance Tested Per JESD 22  
− 2000-V Human-Body Model  
(A114-B, Class II)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
D
D
I
Supports Partial-Power-Down Mode  
off  
Operation  
Schmitt-Trigger Action Allows Slow Input  
Transition and Better Switching Noise  
Immunity at the Input  
D
ESD Protection Exceeds 5000 V With  
Human-Body Model  
(V  
= 250 mV Typ at 3.3 V)  
hys  
DBV OR DCK PACKAGE  
(TOP VIEW)  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
3 4  
2
GND  
B
Y
V
1
2
3
5
4
A
B
GND  
V
Y
CC  
1 5  
A
CC  
description/ordering information  
The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable  
applications. This family ensures a very low static- and dynamic-power consumption across the entire V  
CC  
range of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent  
signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).  
Static-Power Consumption  
Dynamic-Power Consumption  
(pF)  
Switching Characteristics  
†
(µA)  
at 25 MHz  
3.5  
3
100%  
100%  
80%  
60%  
80%  
2.5  
2
Input  
Output  
60%  
40%  
3.3-V  
3.3-V  
†  
Logic  
1.5  
1
†
Logic  
40%  
0.5  
0
20%  
0%  
20%  
0%  
AUP  
AUP  
−0.5  
10  
15 20  
Time − ns  
AUP1G08 data at C = 15 pF  
0
5
25  
35 40 45  
30  
†
Single, dual, and triple gates  
†
L
Figure 2. Excellent Signal Integrity  
Y + A • B or Y + A ) B  
Figure 1. AUP − The Lowest-Power Family  
This single 2-input positive-AND gate performs the Boolean function  
in positive logic.  
NanoStarand NanoFreepackage technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar and NanoFree are trademarks of Texas Instruments.  
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Copyright 2004, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

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