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SN74ALVCHR162601DLR

更新时间： 2024-11-18 13:13:47
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德州仪器 - TI 总线收发器输出元件
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SN74ALVCHR162601DLR 数据手册

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SN74ALVCHR162601  
18-BIT UNIVERSAL BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
SCES123E – SEPTEMBER 1997 – REVISED FEBRUARY 1999  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
OEAB  
LEAB  
A1  
1
56 CLKENAB  
55 CLKAB  
54 B1  
2
UBT (Universal Bus Transceiver)  
3
Combines D-Type Latches and D-Type  
Flip-Flops for Operation in Transparent,  
Latched, Clocked, or Clock-Enabled Mode  
4
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
GND  
A2  
A3  
GND  
B2  
B3  
5
6
Output Ports Have Equivalent 26-Ω Series  
Resistors, So No External Resistors Are  
Required  
7
V
V
CC  
A4  
CC  
8
B4  
B5  
B6  
GND  
B7  
9
A5  
A6  
GND  
A7  
A8  
A9  
A10  
A11  
A12  
GND  
A13  
A14  
A15  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
B8  
B9  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
B10  
B11  
B12  
GND  
B13  
B14  
B15  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
Package Options Include Plastic Thin  
Shrink Small-Outline (DGG), Thin Very  
Small-Outline (DGV), and 300-mil Shrink  
Small-Outline (DL) Packages  
V
V
CC  
CC  
NOTE: For order entry:  
A16  
A17  
GND  
A18  
OEBA  
LEBA  
B16  
B17  
GND  
B18  
CLKBA  
CLKENBA  
The DGG package is abbreviated to G, and  
the DGV package is abbreviated to V.  
description  
This 18-bit universal bus transceiver is designed  
for 1.65-V to 3.6-V V operation.  
CC  
The SN74ALVCHR162601 combines D-type latches and D-type flip-flops to allow data flow in transparent,  
latched, clocked, and clock-enabled modes.  
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),  
and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and  
CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When  
LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored  
in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is low, the outputs are active. When  
OEAB is high, the outputs are in the high-impedance state.  
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA, and CLKENBA.  
The outputs include equivalent 26-Ω series resistors to reduce overshoot and undershoot.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, EPIC, and UBT are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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