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SN74ALVCHR16409

更新时间： 2024-11-17 23:33:59
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9-Bit. 4-Port Universal Bus Exchanger With 3-State Outputs

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SN74ALVCHR16409 数据手册

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SN74ALVCHR16409  
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER  
WITH 3-STATE OUTPUTS  
SCES056G – SEPTEMBER 1995 – REVISED JUNE 1999  
DGG OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus+ Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
PRE  
SEL0  
1A1  
GND  
1A2  
CLK  
SELEN  
1B1  
GND  
1B2  
2
B-Port Outputs Have Equivalent 26-Ω  
Series Resistors, So No External Resistors  
Are Required  
3
4
5
UBE (Universal Bus Exchanger) Allows  
Synchronous Data Exchange  
6
1A3  
1B3  
7
V
V
CC  
CC  
8
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
1A4  
1A5  
1A6  
GND  
1A7  
1A8  
1A9  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
1B4  
1B5  
1B6  
GND  
1B7  
1B8  
1B9  
2B1  
2B2  
2B3  
GND  
2B4  
2B5  
2B6  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
NOTE: For tape and reel order entry:  
The DGGR package is abbreviated to GR, and  
the DLR package is abbreviated to LR.  
V
V
CC  
CC  
2A7  
2A8  
GND  
2A9  
SEL1  
SEL2  
2B7  
2B8  
GND  
2B9  
SEL4  
SEL3  
description  
This 9-bit, 4-port universal bus exchanger is  
designed for 1.65-V to 3.6-V V  
operation.  
CC  
The SN74ALVCHR16409 allows synchronous  
data exchange between four different buses. Data  
flow is controlled by the select (SEL0–SEL4)  
inputs. A data-flow state is stored on the rising  
edge of the clock (CLK) input if the select-enable  
(SELEN) input is low. Once a data-flow state has  
been established, data is stored in the flip-flop on  
the rising edge of CLK if SELEN is high.  
The data-flow control logic is designed to allow glitch-free data transmission.  
The B outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω series resistors to reduce  
overshoot and undershoot.  
When preset (PRE) transitions high, the outputs are disabled immediately, without waiting for a clock pulse. To  
leave the high-impedance state, both PRE and SELEN must be low and a clock pulse must be applied.  
Toensurethehigh-impedancestateduringpoweruporpowerdown,PREshouldbetiedtoV throughapullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC, UBE, and Widebus+ are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

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