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SN74ALVCHR16601GR PDF预览

SN74ALVCHR16601GR

更新时间: 2024-09-15 12:47:03
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
14页 318K
描述
18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

SN74ALVCHR16601GR 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP-56针数:56
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:1.51Is Samacsys:N
控制类型:INDEPENDENT CONTROL计数方向:BIDIRECTIONAL
系列:ALVC/VCX/AJESD-30 代码:R-PDSO-G56
JESD-609代码:e4长度:14 mm
逻辑集成电路类型:REGISTERED BUS TRANSCEIVER最大I(ol):0.012 A
湿度敏感等级:1位数:18
功能数量:1端口数量:2
端子数量:56最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE WITH SERIES RESISTOR
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP56,.3,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TR峰值回流温度(摄氏度):260
电源:3.3 V最大电源电流(ICC):0.04 mA
Prop。Delay @ Nom-Sup:4.4 ns传播延迟(tpd):6.3 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A触发器类型:POSITIVE EDGE
宽度:6.1 mmBase Number Matches:1

SN74ALVCHR16601GR 数据手册

 浏览型号SN74ALVCHR16601GR的Datasheet PDF文件第2页浏览型号SN74ALVCHR16601GR的Datasheet PDF文件第3页浏览型号SN74ALVCHR16601GR的Datasheet PDF文件第4页浏览型号SN74ALVCHR16601GR的Datasheet PDF文件第5页浏览型号SN74ALVCHR16601GR的Datasheet PDF文件第6页浏览型号SN74ALVCHR16601GR的Datasheet PDF文件第7页 
SN74ALVCHR16601  
18-BIT UNIVERSAL BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES123ISEPTEMBER 1997REVISED SEPTEMBER 2004  
FEATURES  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments Widebus™  
Family  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
OEAB  
LEAB  
A1  
GND  
A2  
CLKENAB  
CLKAB  
B1  
GND  
B2  
UBT™ Transceiver Combines D-Type Latches  
and D-Type Flip-Flops for Operation in  
Transparent, Latched, or Clocked Modes  
2
3
4
Operates From 1.65 V to 3.6 V  
Max tpd of 4.4 ns at 3.3 V  
5
6
A3  
B3  
±12-mA Output Drive at 3.3 V  
7
V
CC  
V
CC  
Outputs Ports Have Equivalent 26-Series  
Resistors, So No External Resistors Are  
Required  
8
A4  
A5  
A6  
GND  
A7  
A8  
B4  
B5  
B6  
GND  
B7  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
B8  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
A9  
B9  
A10  
A11  
A12  
GND  
A13  
A14  
A15  
B10  
B11  
B12  
GND  
B13  
B14  
B15  
ESD Protection Exceeds JESD 22  
- 2000-V Human-Body Model (A114-A)  
- 200-V Machine Model (A115-A)  
DESCRIPTION/ORDERING INFORMATION  
This 18-bit universal bus transceiver is designed for  
1.65-V to 3.6-V VCC operation.  
V
CC  
V
CC  
The SN74ALVCHR16601 combines D-type latches  
and D-type flip-flops to allow data flow in transparent,  
latched, clocked, and clock-enabled modes.  
A16  
A17  
B16  
B17  
GND  
A18  
OEBA  
LEBA  
GND  
B18  
CLKBA  
CLKENBA  
Data flow in each direction is controlled by  
output-enable (OEAB and OEBA), latch-enable  
(LEAB and LEBA), and clock (CLKAB and CLKBA)  
inputs. The clock can be controlled by the  
clock-enable (CLKENAB and CLKENBA) inputs. For  
A-to-B data flow, the device operates in the  
transparent mode when LEAB is high. When LEAB is  
low, the A data is latched if CLKAB is held at a high  
or low logic level. If LEAB is low, the A data is stored  
in the latch/flip-flop on the low-to-high transition of  
CLKAB. When OEAB is low, the outputs are active.  
When OEAB is high, the outputs are in the  
high-impedance state.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74ALVCHR16601DL  
SN74ALVCHR16601LR  
SN74ALVCHR16601GR  
SN74ALVCHR16601VR  
TOP-SIDE MARKING  
Tube  
SSOP - DL  
ALVCHR16601  
Tape and reel  
Tape and reel  
Tape and reel  
-40°C to 85°C  
TSSOP - DGG  
TVSOP - DGV  
ALVCHR16601  
VR601  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, UBT are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1997–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

SN74ALVCHR16601GR 替代型号

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