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SN74ALVCHR16601LR

更新时间： 2024-11-06 12:47:03
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德州仪器 - TI 总线收发器输出元件
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14页 318K
描述
18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

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SN74ALVCHR16601LR 数据手册

 浏览型号SN74ALVCHR16601LR的Datasheet PDF文件第2页浏览型号SN74ALVCHR16601LR的Datasheet PDF文件第3页浏览型号SN74ALVCHR16601LR的Datasheet PDF文件第4页浏览型号SN74ALVCHR16601LR的Datasheet PDF文件第5页浏览型号SN74ALVCHR16601LR的Datasheet PDF文件第6页浏览型号SN74ALVCHR16601LR的Datasheet PDF文件第7页 
SN74ALVCHR16601  
18-BIT UNIVERSAL BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES123I–SEPTEMBER 1997–REVISED SEPTEMBER 2004  
FEATURES  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
•
Member of the Texas Instruments Widebus™  
Family  
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56  
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40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
OEAB  
LEAB  
A1  
GND  
A2  
CLKENAB  
CLKAB  
B1  
GND  
B2  
•
UBT™ Transceiver Combines D-Type Latches  
and D-Type Flip-Flops for Operation in  
Transparent, Latched, or Clocked Modes  
2
3
4
•
•
•
•
Operates From 1.65 V to 3.6 V  
Max tpd of 4.4 ns at 3.3 V  
5
6
A3  
B3  
±12-mA Output Drive at 3.3 V  
7
V
CC  
V
CC  
Outputs Ports Have Equivalent 26-Ω Series  
Resistors, So No External Resistors Are  
Required  
8
A4  
A5  
A6  
GND  
A7  
A8  
B4  
B5  
B6  
GND  
B7  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
•
•
•
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
B8  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
A9  
B9  
A10  
A11  
A12  
GND  
A13  
A14  
A15  
B10  
B11  
B12  
GND  
B13  
B14  
B15  
ESD Protection Exceeds JESD 22  
- 2000-V Human-Body Model (A114-A)  
- 200-V Machine Model (A115-A)  
DESCRIPTION/ORDERING INFORMATION  
This 18-bit universal bus transceiver is designed for  
1.65-V to 3.6-V VCC operation.  
V
CC  
V
CC  
The SN74ALVCHR16601 combines D-type latches  
and D-type flip-flops to allow data flow in transparent,  
latched, clocked, and clock-enabled modes.  
A16  
A17  
B16  
B17  
GND  
A18  
OEBA  
LEBA  
GND  
B18  
CLKBA  
CLKENBA  
Data flow in each direction is controlled by  
output-enable (OEAB and OEBA), latch-enable  
(LEAB and LEBA), and clock (CLKAB and CLKBA)  
inputs. The clock can be controlled by the  
clock-enable (CLKENAB and CLKENBA) inputs. For  
A-to-B data flow, the device operates in the  
transparent mode when LEAB is high. When LEAB is  
low, the A data is latched if CLKAB is held at a high  
or low logic level. If LEAB is low, the A data is stored  
in the latch/flip-flop on the low-to-high transition of  
CLKAB. When OEAB is low, the outputs are active.  
When OEAB is high, the outputs are in the  
high-impedance state.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74ALVCHR16601DL  
SN74ALVCHR16601LR  
SN74ALVCHR16601GR  
SN74ALVCHR16601VR  
TOP-SIDE MARKING  
Tube  
SSOP - DL  
ALVCHR16601  
Tape and reel  
Tape and reel  
Tape and reel  
-40°C to 85°C  
TSSOP - DGG  
TVSOP - DGV  
ALVCHR16601  
VR601  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, UBT are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1997–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...14

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