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SN74ALVCHR16269A

更新时间： 2024-09-15 23:09:43
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德州仪器 - TI 输出元件
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12页 177K
描述
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS

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SN74ALVCHR16269A 数据手册

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SN74ALVCHR16269A  
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES050O–AUGUST 1995–REVISED SEPTEMBER 2004  
FEATURES  
DGG, DGV, OR DL PACKAGE  
•
Member of the Texas Instruments Widebus™  
(TOP VIEW)  
Family  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
OEA  
OEB1  
2B3  
GND  
2B2  
OEB2  
CLKENA2  
2B4  
GND  
2B5  
•
•
•
•
Operates From 1.65 V to 3.6 V  
Max tpd of 5.2 ns at 3.3 V  
±24-mA Output Drive at 3.3 V  
2
3
4
All Outputs Have Equivalent 26-Ω Series  
Resistors, So No External Resistors Are  
Required  
5
6
2B1  
2B6  
7
V
CC  
V
CC  
•
•
•
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
8
A1  
A2  
A3  
GND  
A4  
A5  
2B7  
2B8  
2B9  
9
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
GND  
2B10  
2B11  
2B12  
1B12  
1B11  
1B10  
GND  
1B9  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
A6  
A7  
A8  
A9  
GND  
A10  
A11  
A12  
DESCRIPTION/ORDERING INFORMATION  
This 12-bit to 24-bit registered bus exchanger is  
designed for 1.65-V to 3.6-V VCC operation.  
1B8  
1B7  
The SN74ALVCHR16269A is used in applications in  
which two ports must be multiplexed onto, or  
demultiplexed from, a single port. It is particularly  
suitable as an interface between synchronous  
DRAMs and high-speed microprocessors.  
V
CC  
V
CC  
1B1  
1B2  
GND  
1B3  
NC  
1B6  
1B5  
GND  
1B4  
CLKENA1  
CLK  
Data is stored in the internal B-port registers on the  
low-to-high transition of the clock (CLK) input, when  
the appropriate clock-enable (CLKENA) inputs are  
low. Proper control of these inputs allows two  
sequential 12-bit words to be presented as a 24-bit  
word on the B port. For data transfer in the B-to-A  
SEL  
NC − No internal connection  
direction, a single storage register is provided. The select (SEL) line selects 1B or 2B data for the A outputs. The  
register on the A output permits the fastest possible data transfer, thus extending the period during which the  
data is valid on the bus. The control terminals are registered so that all transactions are synchronous with CLK.  
Data flow is controlled by the active-low output enables (OEA, OEB1, and OEB2).  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74ALVCHR16269AL  
TOP-SIDE MARKING  
Tube  
SSOP – DL  
ALVCHR16269A  
Tape and reel  
SN74ALVCHR16269ALR  
SN74ALVCHR16269AGR  
SN74ALVCHR16269AVR  
-40°C to 85°C  
TSSOP – DGG  
TVSOP – DGV  
Tape and reel  
Tape and reel  
ALVCHR16269A  
VR269A  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1995–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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