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SN74ALVC3631-10PCB PDF预览

SN74ALVC3631-10PCB

更新时间： 2024-09-17 02:58:43
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德州仪器 - TI /
页数 文件大小 规格书
28页 438K
描述
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES

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SN74ALVC3631-10PCB 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LFQFP, QFP120,.63SQ,16针数：120
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.32.00.71Factory Lead Time：1 week
风险等级：5.85最长访问时间：7.5 ns
周期时间：10 nsJESD-30 代码：S-PQFP-G120
长度：14 mm内存密度：18432 bit
内存集成电路类型：BI-DIRECTIONAL FIFO内存宽度：36
功能数量：1端子数量：120
字数：512 words字数代码：512
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：512X36
可输出：YES封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装等效代码：QFP120,.63SQ,16
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm子类别：FIFOs
最大压摆率：0.00035 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：GULL WING
端子节距：0.4 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm

SN74ALVC3631-10PCB 数据手册

 浏览型号SN74ALVC3631-10PCB的Datasheet PDF文件第2页浏览型号SN74ALVC3631-10PCB的Datasheet PDF文件第3页浏览型号SN74ALVC3631-10PCB的Datasheet PDF文件第4页浏览型号SN74ALVC3631-10PCB的Datasheet PDF文件第5页浏览型号SN74ALVC3631-10PCB的Datasheet PDF文件第6页浏览型号SN74ALVC3631-10PCB的Datasheet PDF文件第7页 
SN74ALVC3631, SN74ALVC3641, SN74ALVC3651  
512 × 36, 1024 × 36, 2048 × 36  
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES  
SDMS025B – OCTOBER 1999 – REVISED JUNE 2000  
Free-Running CLKA and CLKB Can Be  
Asynchronous or Coincident  
Output-Ready and AE Flags Synchronized  
by CLKB  
Clocked FIFO Buffering Data From Port A  
to Port B  
Low-Power 0.8-µm Advanced CMOS  
Technology  
Synchronous Read-Retransmit Capability  
Mailbox Register in Each Direction  
Supports Clock Frequencies up to 100 MHz  
Fast Access Times of 6.5 ns  
Programmable Almost-Full (AF) and  
Almost-Empty (AE) Flags  
Pin-to-Pin Compatible With 5-V Operating  
SN74ACT3631, SN74ACT3641, and  
SN74ACT3651  
Microprocessor Interface Control Logic  
Package Options Include 120-Pin Thin  
Quad Flat (PCB) and 132-Pin Plastic Quad  
Flat (PQ) Packages  
Input-Ready and AF Flags Synchronized by  
CLKA  
description  
The SN74ALVC3631, SN74ALVC3641, and SN74ALVC3651 are high-speed, low-power, CMOS, synchronous  
FIFO memories that support clock frequencies up to 100 MHz and have read access times as fast as 6.5 ns.  
The 512 × 36, 1024 × 36, and 2048 × 36 dual-port SRAM FIFOs buffer data from port A to port B. The FIFO  
memories have retransmit capability, which allows previously read data to be accessed again. The FIFOs have  
flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate  
when a selected number of words is stored in memory. Communication between each port takes place with two  
36-bit mailbox registers. Each mailbox register has a flag that signals when new mail has been stored. Two or  
more devices are used in parallel to create wider data paths. Expansion also is possible in word depth.  
The SN74ALVC3631/41/51 are synchronous FIFOs, which means each port employs a synchronous interface.  
All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock  
by enable signals. The continuous clocks for each port are independent of one another and can be  
asynchronous or coincident. The enables for each port are arranged to provide a simple interface between  
microprocessors and/or buses with synchronous control.  
The input-ready (IR) flag and almost-full (AF) flag of the FIFOs are two-stage, synchronized to CLKA. The  
output-ready (OR) flag and almost-empty (AE) flag of the FIFOs are two-stage, synchronized to CLKB. Offset  
values for AF and AE are programmed from port A or through a serial input.  
The SN74ALVC3631/41/51 are characterized for operation from 0°C to 70°C.  
For more information on this device family, see the following application reports:  
FIFO Patented Synchronous Retransmit: Programmable DSP-Interface Application for FIR Filtering  
(literature number SCAA009)  
FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control  
(literature number SCAA007)  
Metastability Performance of Clocked FIFOs (literature number SCZA004)  
FIFO Architecture, Functions, and Applications (literature number SCAA042)  
Optimizing DSP-Based Digital Filters With Application-Specific FIFOs (literature number SCAA021)  
FIFO Memories: Surface-Mount Packages for PCMCIA Applications (literature number SDMA001A)  
Interfacing TI Clocked FIFOs with TI Floating-Point DSPs (literature number SCAA005A)  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...28

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与SN74ALVC3631-10PCB相关器件

型号 品牌 获取价格 描述 数据表
SN74ALVC3631-10PQ ROCHESTER

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 		512X36 OTHER FIFO, 7.5ns, PQFP132, PLASTIC, BQFP-132
SN74ALVC3631-10PQ TI

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 		SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SN74ALVC3631-15PCB ROCHESTER

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 		512X36 OTHER FIFO, 9.5ns, PQFP120, PLASTIC, HLQFP-120
SN74ALVC3631-15PCB TI

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 		SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SN74ALVC3631-15PQ TI

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 		512 x 36 3.3-V synchronous FIFO memory 132-BQFP 0 to 70
SN74ALVC3631-15PQ ROCHESTER

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 		512X36 OTHER FIFO, 9.5ns, PQFP132, PLASTIC, BQFP-132
SN74ALVC3631-15PQR TI

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 		512 X 36 OTHER FIFO, 9.5 ns, PQFP132, PLASTIC, BQFP-132
SN74ALVC3631-20PCB TI

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 		512 x 36 3.3-V synchronous FIFO memory 120-HLQFP 0 to 70
SN74ALVC3631-20PCB ROCHESTER

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 		512X36 OTHER FIFO, 11.5ns, PQFP120, PLASTIC, HLQFP-120
SN74ALVC3631-20PQ TI

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 		512 x 36 3.3-V synchronous FIFO memory 132-BQFP 0 to 70

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