Datasheet > SN74ALVC3651-10PQR

SN74ALVC3651-10PQR

更新时间： 2024-09-16 15:52:07

品牌	Logo	应用领域
德州仪器 - TI		先进先出芯片
页数	文件大小	规格书
29页	462K
描述
2KX36 OTHER FIFO, 7.5ns, PQFP132, PLASTIC, BQFP-132

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SN74ALVC3651-10PQR 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	QFP,	针数：	132
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	风险等级：	5.78
最长访问时间：	7.5 ns	其他特性：	RETRANSMIT; MAILBOX
周期时间：	10 ns	JESD-30 代码：	S-PQFP-G132
长度：	24.13 mm	内存密度：	73728 bit
内存宽度：	36	功能数量：	1
端子数量：	132	字数：	2048 words
字数代码：	2000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	2KX36	可输出：	YES
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装形状：	SQUARE	封装形式：	FLATPACK
并行/串行：	PARALLEL	认证状态：	Not Qualified
座面最大高度：	4.57 mm	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.635 mm	端子位置：	QUAD
宽度：	24.13 mm	Base Number Matches：	1

SN74ALVC3651-10PQR 数据手册

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SN74ALVC3631, SN74ALVC3641, SN74ALVC3651

512 × 36, 1024 × 36, 2048 × 36

SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES

SDMS025B – OCTOBER 1999 – REVISED JUNE 2000

Free-Running CLKA and CLKB Can Be

Asynchronous or Coincident

Output-Ready and AE Flags Synchronized

by CLKB

Clocked FIFO Buffering Data From Port A

to Port B

Low-Power 0.8-µm Advanced CMOS

Technology

Synchronous Read-Retransmit Capability

Mailbox Register in Each Direction

Supports Clock Frequencies up to 100 MHz

Fast Access Times of 6.5 ns

Programmable Almost-Full (AF) and

Almost-Empty (AE) Flags

Pin-to-Pin Compatible With 5-V Operating

SN74ACT3631, SN74ACT3641, and

SN74ACT3651

Microprocessor Interface Control Logic

Package Options Include 120-Pin Thin

Quad Flat (PCB) and 132-Pin Plastic Quad

Flat (PQ) Packages

Input-Ready and AF Flags Synchronized by

CLKA

description

The SN74ALVC3631, SN74ALVC3641, and SN74ALVC3651 are high-speed, low-power, CMOS, synchronous

FIFO memories that support clock frequencies up to 100 MHz and have read access times as fast as 6.5 ns.

The 512 × 36, 1024 × 36, and 2048 × 36 dual-port SRAM FIFOs buffer data from port A to port B. The FIFO

memories have retransmit capability, which allows previously read data to be accessed again. The FIFOs have

flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate

when a selected number of words is stored in memory. Communication between each port takes place with two

36-bit mailbox registers. Each mailbox register has a flag that signals when new mail has been stored. Two or

more devices are used in parallel to create wider data paths. Expansion also is possible in word depth.

The SN74ALVC3631/41/51 are synchronous FIFOs, which means each port employs a synchronous interface.

All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock

by enable signals. The continuous clocks for each port are independent of one another and can be

asynchronous or coincident. The enables for each port are arranged to provide a simple interface between

microprocessors and/or buses with synchronous control.

The input-ready (IR) flag and almost-full (AF) flag of the FIFOs are two-stage, synchronized to CLKA. The

output-ready (OR) flag and almost-empty (AE) flag of the FIFOs are two-stage, synchronized to CLKB. Offset

values for AF and AE are programmed from port A or through a serial input.

The SN74ALVC3631/41/51 are characterized for operation from 0°C to 70°C.

For more information on this device family, see the following application reports:

FIFO Patented Synchronous Retransmit: Programmable DSP-Interface Application for FIR Filtering

(literature number SCAA009)

FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control

(literature number SCAA007)

Metastability Performance of Clocked FIFOs (literature number SCZA004)

FIFO Architecture, Functions, and Applications (literature number SCAA042)

Optimizing DSP-Based Digital Filters With Application-Specific FIFOs (literature number SCAA021)

FIFO Memories: Surface-Mount Packages for PCMCIA Applications (literature number SDMA001A)

Interfacing TI Clocked FIFOs with TI Floating-Point DSPs (literature number SCAA005A)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...29

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与SN74ALVC3651-10PQR相关器件

型号	品牌	获取价格	描述	数据表
SN74ALVC3651-15PCB	TI	获取价格	2048 x 36 3.3-V synchronous FIFO memory 120-HLQFP 0 to 70
SN74ALVC3651-15PCBR	TI	获取价格	2KX36 OTHER FIFO, 9.5ns, PQFP120, PLASTIC, HLQFP-120
SN74ALVC3651-15PQ	TI	获取价格	2048 x 36 3.3-V synchronous FIFO memory 132-BQFP 0 to 70
SN74ALVC3651-15PQR	TI	获取价格	2KX36 OTHER FIFO, 9.5ns, PQFP132, PLASTIC, BQFP-132
SN74ALVC3651-20PCBR	TI	获取价格	2KX36 OTHER FIFO, 11.5ns, PQFP120, PLASTIC, HLQFP-120
SN74ALVC3651-20PQ	ROCHESTER	获取价格	2KX36 OTHER FIFO, 11.5ns, PQFP132, PLASTIC, BQFP-132
SN74ALVC3651-20PQ	TI	获取价格	暂无描述
SN74ALVC3651-20PQR	TI	获取价格	2KX36 OTHER FIFO, 11.5ns, PQFP132, PLASTIC, BQFP-132
SN74ALVC3651PCB	TI	获取价格	2048 】 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEM
SN74ALVC3651PQ	TI	获取价格	2048 】 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEM

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