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SN74ALS234FN

更新时间： 2024-09-26 13:13:47
品牌 Logo 应用领域
德州仪器 - TI 存储
页数 文件大小 规格书
11页 206K
描述
64X4 OTHER FIFO, 22ns, PQCC20

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中文翻译

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SN74ALS234FN 技术参数

是否Rohs认证：不符合生命周期：Obsolete
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.82
Is Samacsys：N最长访问时间：22 ns
最大时钟频率 (fCLK)：30 MHz周期时间：33.33 ns
JESD-30 代码：S-PQCC-J20长度：8.9662 mm
内存密度：256 bit内存集成电路类型：OTHER FIFO
内存宽度：4功能数量：1
端子数量：20字数：64 words
字数代码：64工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：64X4输出特性：3-STATE
可输出：YES封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC20,.4SQ
封装形状：SQUARE封装形式：CHIP CARRIER
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified座面最大高度：4.57 mm
子类别：FIFOs最大压摆率：0.148 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：TTL温度等级：COMMERCIAL
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：8.9662 mmBase Number Matches：1

SN74ALS234FN 数据手册

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SDAS106B − OCTOBER 1986 − REVISED SEPTEMBER 1993  
DW OR N PACKAGE  
(TOP VIEW)  
D Asynchronous Operation  
D Organized as 64 Words by 4 Bits  
D Data Rates From 0 to 30 MHz  
D 3-State Outputs  
V
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IR  
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D Package Options Include Plastic  
Small-Outline Packages (DW), Plastic  
J-Leaded Chip Carriers (FN), and Standard  
Plastic 300-mil DIPs (N)  
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description  
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GND  
The SN74ALS234 is a 256-bit memory utilizing  
advanced low-power Schottky IMPACT  
technology. It features high speed with fast  
fall-through times and is organized as 64 words by  
4 bits.  
FN PACKAGE  
(TOP VIEW)  
A first-in, first-out (FIFO) memory is a storage  
device that allows data to be written into and read  
from its array at independent data rates. The  
SN74ALS234 is designed to process data at rates  
from 0 to 30 MHz in a bit-parallel format, word by  
word.  
3
2 1 20 19  
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Data is written into memory on the rising edge of  
the shift-in (SI) input. When SI goes low, the first  
data word ripples through to the output (see  
Figure 1). As the FIFO fills up, the data words  
stack up in the order they were written. When the  
FIFO is full, additional shift-in pulses have no  
NC − No internal connection  
effect. Data is shifted out of memory on the falling edge of the shift-out (SO) input (see Figure 2). When the FIFO  
is empty, additional SO pulses have no effect. The last data word remains at the outputs until a new word falls  
through or reset (RST) goes low.  
Status of the SN74ALS234 FIFO memory is monitored by the output-ready (OR) and input-ready (IR) flags.  
When OR is high, valid data is available at the outputs. OR is low when SO is high and stays low when the FIFO  
is empty. IR is high when the inputs are ready to receive more data. IR is low when SI is high and stays low when  
the FIFO is full.  
When the FIFO is empty, input data is shifted to the output automatically when SI goes low. If SO is held high  
during this time, the OR flag pulses high indicating valid data at the outputs (see Figure 3).  
When the FIFO is full, data can be shifted in automatically by holding SI high and taking SO low. One propagation  
delay after SO goes low, IR will go high. If SI is still high when IR goes high, data at the inputs are automatically  
shifted in. Since IR is normally low when the FIFO is full and SI is high, only a high-level pulse is seen on the  
IR output (see Figure 4).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
IMPACT is a trademark of Texas Instruments Incorporated.  
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Copyright 1993, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...11

中文翻译

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