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SN74ALS235N PDF预览

SN74ALS235N

更新时间: 2024-11-29 20:54:47
品牌 Logo 应用领域
德州仪器 - TI 时钟先进先出芯片光电二极管内存集成电路
页数 文件大小 规格书
15页 242K
描述
64 x 5 Asynchronous FIFO memory 20-PDIP 0 to 70

SN74ALS235N 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP20,.3针数:20
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.66
最长访问时间:22 ns最大时钟频率 (fCLK):25 MHz
周期时间:40 nsJESD-30 代码:R-PDIP-T20
长度:24.325 mm内存密度:320 bit
内存集成电路类型:OTHER FIFO内存宽度:5
功能数量:1端子数量:20
字数:64 words字数代码:64
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:64X5
输出特性:3-STATE可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP20,.3封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:5.08 mm子类别:FIFOs
最大压摆率:0.17 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

SN74ALS235N 数据手册

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SN74ALS235  
64 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY  
SDAS108A – OCTOBER 1986 – REVISED SEPTEMBER 1993  
DW OR N PACKAGE  
(TOP VIEW)  
Asynchronous Operation  
Organized as 64 Words by 5 Bits  
Data Rates From 0 to 25 MHz  
3-State Outputs  
OE  
HF  
IR  
V
CC  
AF/AE  
1
2
3
4
5
6
7
8
9
20  
19  
18  
17  
16  
15  
14  
SO  
OR  
Q0  
Q1  
Q2  
Package Options Include Plastic  
Small-Outline Packages (DW), Plastic  
J-Leaded Chip Carriers (FN), and Standard  
Plastic 300-mil DIPs (N)  
SI  
D0  
D1  
D2  
D3  
D4  
13 Q3  
12 Q4  
11 RST  
description  
The SN74ALS235 is a 320-bit memory utilizing  
advanced low-power Schottky IMPACT  
technology. It features high speed with fast  
fall-through times and is organized as 64 words by  
5 bits.  
GND 10  
FN PACKAGE  
(TOP VIEW)  
A first-in, first-out (FIFO) memory is a storage  
device that allows data to be written into and read  
from its array at independent data rates. The  
SN74ALS235 is designed to process data at rates  
from 0 to 25 MHz in a bit-parallel format, word by  
word.  
3
2
1
20 19  
18  
SI  
D0  
D1  
D2  
D3  
SO  
OR  
Q0  
Q1  
Q2  
4
5
6
7
8
17  
16  
15  
14  
Data is written into memory on the rising edge of  
the shift-in (SI) input. When SI goes low, the first  
data word ripples through to the output (see  
Figure 1). As the FIFO fills up, the data words  
stack up in the order they were written. When the  
FIFO is full, additional shift-in pulses have no  
9 10 11 12 13  
effect. Data is shifted out of memory on the falling edge of the shift-out (SO) input (see Figure 2). When the FIFO  
is empty, additional SO pulses have no effect. The last data word remains at the outputs until a new word falls  
through or reset (RST) goes low.  
Status of the SN74ALS235 FIFO memory is monitored by the output-ready (OR), input-ready (IR),  
almost-full/almost-empty (AF/AE), and half-full (HF) flags. When OR is high, valid data is available at the  
outputs. OR is low when SO is high and stays low when the FIFO is empty. IR is high when the inputs are ready  
to receive more data. IR is low when SI is high and stays low when the FIFO is full. AF/AE is high when the FIFO  
contains eight or less words (see Figure 5) or 56 or more words (see Figure 6). AF/AE is low when the FIFO  
contains between nine and 55 words. HF is high when the FIFO contains 32 or more words and is low when  
the FIFO contains 31 words or less (see Figure 7).  
When the FIFO is empty, input data is shifted to the output automatically when SI goes low. If SO is held high  
during this time, the OR flag pulses high indicating valid data at the outputs (see Figure 3).  
WhentheFIFOisfull, datacanbeshiftedinautomaticallybyholdingSIhighandtakingSOlow. Onepropagation  
delay after SO goes low, IR will go high. If SI is still high when IR goes high, data at the inputs are automatically  
shifted in. Since IR is normally low when the FIFO is full and SI is high, only a high-level pulse is seen on the  
IR output.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
IMPACT is a trademark of Texas Instruments Incorporated.  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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