5秒后页面跳转
捷配首页

Datasheet > 存储 > FIFO> SN74ALS236FN
SN74ALS236FN PDF预览

SN74ALS236FN

更新时间： 2024-11-13 23:06:15
品牌 Logo 应用领域
德州仪器 - TI 存储内存集成电路先进先出芯片时钟
页数 文件大小 规格书
11页 176K
描述
64 】 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY

阅读下载

中文翻译

获取价格

SN74ALS236FN 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QLCC包装说明：QCCJ, LDCC20,.4SQ
针数：20Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.32.00.71
风险等级：5.91最长访问时间：22 ns
最大时钟频率 (fCLK)：30 MHz周期时间：33.33 ns
JESD-30 代码：S-PQCC-J20长度：8.9662 mm
内存密度：256 bit内存集成电路类型：OTHER FIFO
内存宽度：4功能数量：1
端子数量：20字数：64 words
字数代码：64工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：64X4输出特性：3-STATE
可输出：NO封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC20,.4SQ
封装形状：SQUARE封装形式：CHIP CARRIER
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V认证状态：Not Qualified
座面最大高度：4.57 mm子类别：FIFOs
最大压摆率：0.145 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：TTL
温度等级：COMMERCIAL端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：8.9662 mm
Base Number Matches：1

SN74ALS236FN 数据手册

 浏览型号SN74ALS236FN的Datasheet PDF文件第2页浏览型号SN74ALS236FN的Datasheet PDF文件第3页浏览型号SN74ALS236FN的Datasheet PDF文件第4页浏览型号SN74ALS236FN的Datasheet PDF文件第5页浏览型号SN74ALS236FN的Datasheet PDF文件第6页浏览型号SN74ALS236FN的Datasheet PDF文件第7页 
SN74ALS236  
64 × 4  
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY  
SDAS107C – OCTOBER 1986 – REVISED APRIL 1998  
DW OR N PACKAGE  
(TOP VIEW)  
Asynchronous Operation  
Organized as 64 Words by 4 Bits  
Data Rates up to 30 MHz  
3-State Outputs  
V
NC  
IR  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC  
SO  
OR  
Q0  
SI  
D0  
Package Options Include Plastic  
Small-Outline Package (DW), Plastic  
J-Leaded Chip Carriers (FN), and Standard  
Plastic 300-mil DIPs (N)  
Q1  
D1  
Q2  
D2  
Q3  
D3  
description  
RST  
GND  
The SN74ALS236 is a 256-bit memory utilizing  
advanced low-power Schottky IMPACT  
technology. It features high speed with fast  
fall-through times and is organized as 64 words by  
4 bits.  
FN PACKAGE  
(TOP VIEW)  
A first-in, first-out (FIFO) memory is a storage  
device that allows data to be written into and read  
from its array at independent data rates. The  
SN74ALS236 is designed to process data at rates  
up to 30 MHz in a bit-parallel format, word by  
word.  
3
2 1 20 19  
SI  
OR  
Q0  
NC  
Q1  
Q2  
18  
17  
16  
15  
14  
4
5
6
7
8
D0  
NC  
D1  
D2  
9 10 11 12 13  
Data is written into memory on the rising edge of  
the shift-in (SI) input. When SI goes low, the first  
data word ripples through to the output (see  
Figure 1). As the FIFO fills up, the data words  
stack up in the order they were written. When the  
FIFO is full, additional shift-in pulses have no  
effect. Data is shifted out of memory on the falling  
NC – No internal connection  
edge of the shift-out (SO) input (see Figure 2). When the FIFO is empty, additional SO pulses have no effect.  
The last data word remains at the outputs until a new word falls through or reset (RST) goes low.  
Status of the SN74ALS236 FIFO memory is monitored by the output-ready (OR) and input-ready (IR) flags.  
When OR is high, valid data is available at the outputs. OR is low when SO is high and stays low when the FIFO  
is empty. IR is high when the inputs are ready to receive more data. IR is low when SI is high and stays low when  
the FIFO is full.  
When the FIFO is empty, input data is shifted to the output automatically when SI goes low. If SO is held high  
during this time, the OR flag pulses high, indicating valid data at the outputs (see Figure 3).  
When the FIFO is full, data is shifted in automatically by holding SI high and taking SO low. One propagation  
delay after SO goes low, IR goes high. If SI is still high when IR goes high, data at the inputs is automatically  
shifted in. Since IR is normally low when the FIFO is full and SI is high, only a high-level pulse is seen on the  
IR output (see Figure 4).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
IMPACT is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

中文翻译

下载PDF

与SN74ALS236FN相关器件

型号 品牌 获取价格 描述 数据表
SN74ALS236FN3 TI

获取价格

 		IC,FIFO,64X4,ASYNCHRONOUS,TTL,LDCC,20PIN,PLASTIC
SN74ALS236FNR TI

获取价格

 		64X4 OTHER FIFO, 22ns, PQCC20, PLASTIC, LCC-20
SN74ALS236N TI

获取价格

 		64 】 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMOR
SN74ALS236N3 TI

获取价格

 		IC,FIFO,64X4,ASYNCHRONOUS,TTL,DIP,16PIN,PLASTIC
SN74ALS240A TI

获取价格

 		OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN74ALS240A-1 TI

获取价格

 		OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN74ALS240A-1DB TI

获取价格

 		IC,BUFFER/DRIVER,DUAL,4-BIT,ALS-TTL,SSOP,20PIN,PLASTIC
SN74ALS240A-1DBR TI

获取价格

 		OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN74ALS240A-1DBRE4 TI

获取价格

 		OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN74ALS240A-1DBRG4 TI

获取价格

 		OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

与SN74ALS236FN相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证