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SN74ALS165

更新时间： 2024-11-11 23:06:15
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德州仪器 - TI /
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7页 116K
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PARALLEL-LOAD 8-BIT REGISTERS

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SN74ALS165 数据手册

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SN54ALS165, SN74ALS165  
PARALLEL-LOAD 8-BIT REGISTERS  
SDAS157B – JUNE 1982 – REVISED DECEMBER 1994  
SN54ALS165 . . . J PACKAGE  
SN74ALS165 . . . D OR N PACKAGE  
(TOP VIEW)  
• Complementary Outputs  
• Direct Overriding Load (Data) Inputs  
• Gated Clock Inputs  
SH/LD  
V
CC  
• Parallel-to-Serial Data Conversion  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CLK  
E
CLK INH  
D
• Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
F
C
G
B
H
A
Q
SER  
description  
H
GND  
Q
H
The ′ALS165 are parallel-load 8-bit serial shift  
registers that, when clocked, shift the data toward  
serial (Q and Q ) outputs. Parallel-in access to  
SN54ALS165 . . . FK PACKAGE  
(TOP VIEW)  
H
H
each stage is provided by eight individual direct  
data (A–H) inputs that are enabled by a low level  
at the shift/load (SH/LD) input. The ′ALS165 have  
a clock-inhibit function and complemented serial  
outputs.  
3
2
1
20 19  
18  
E
F
D
4
5
6
7
8
Clocking is accomplished by a low-to-high  
transition of the clock (CLK) input while SH/LD is  
held high and the clock inhibit (CLK INH) input is  
held low. The functions of CLK and CLK INH are  
interchangeable. Since a low CLK and a  
low-to-high transition of CLK INH also  
accomplishes clocking, CLK INH should be  
changed to the high level only while CLK is high.  
Parallel loading is inhibited when SH/LD is held  
high. The parallel inputs to the register are  
enabled while SH/LD is low independently of the  
levels of the CLK, CLK INH, or serial (SER) inputs.  
17  
16  
15  
14  
C
NC  
G
NC  
B
H
A
9 10 11 12 13  
NC – No internal connection  
The SN54ALS165 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74ALS165 is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
FUNCTION  
CLK CLK INH  
SH/LD  
L
X
H
X
L
X
X
H
↑
Parallel load  
No change  
No change  
H
H
H
H
†
Shift  
Shift  
†
↑
L
†
Shift = content of each internal register shifts  
toward serial outputs. Data at SER is shifted  
into first register.  
Copyright 1994, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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SN74ALS165 替代型号

型号 品牌 替代类型 描述 数据表
SN54ALS165 TI

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 PARALLEL-LOAD 8-BIT REGISTERS

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