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SN74ALS166D

更新时间： 2024-09-29 23:06:15
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德州仪器 - TI 移位寄存器
页数 文件大小 规格书
11页 343K
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PARALLEL-LOAD 8-BIT SHIFT REGISTER

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SN74ALS166D 数据手册

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SN74ALS166  
PARALLEL-LOAD 8-BIT SHIFT REGISTER  
SDAS156D – APRIL 1982 – REVISED AUGUST 2000  
D, DB, OR N PACKAGE  
(TOP VIEW)  
Synchronous Load  
Direct Overriding Clear  
Parallel-to-Serial Conversion  
SER  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
A
SH/LD  
Package Options Include Plastic  
Small-Outline (D) and Shrink Small-Outline  
(DB) Packages and Standard Plastic (N) DIP  
B
C
H
Q
H
D
G
description  
CLK INH  
CLK  
F
E
The SN74ALS166 parallel-load 8-bit shift register  
is compatible with most other TTL logic families.  
All inputs are buffered to lower the drive  
requirements. Input clamping diodes minimize  
switching transients and simplify system design.  
GND  
CLR  
These parallel-in or serial-in, serial-out registers have a complexity of 77 equivalent gates on the chip. They  
feature gated clocks (CLK and CLK INH) inputs and an overriding clear (CLR) input. The parallel-in or serial-in  
modes are established by the shift/load (SH/LD) input. When high, SH/LD enables the serial data (SER) input  
and couples the eight flip-flops for serial shifting with each clock pulse. When low, the parallel (broadside) data  
(A–H)inputsareenabledandsynchronousloadingoccursonthenextclockpulse. Duringparallelloading, serial  
data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of the clock pulse through a  
two-input positive-NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding  
either of the clock inputs high inhibits clocking; holding either low enables the other clock input. This allows the  
system clock to be free running and the register can be stopped on command with the clock input. CLK INH  
shouldbechangedtothehighlevelonlywhenCLKishigh. ThebufferedCLRoverridesallotherinputs, including  
CLK, and sets all flip-flops to zero.  
The SN74ALS166 is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
INTERNAL  
OUTPUTS  
OUTPUT  
PARALLEL  
Q
CLR  
SH/LD  
CLK  
CLK INH  
SER  
H
A . . . H  
Q
Q
B
A
L
X
X
L
X
L
L
L
L
H
X
L
↑
↑
↑
↑
X
X
X
H
L
X
L
L
L
H
H
H
H
H
X
Q
Q
Q
H0  
h
A0  
B0  
a . . . h  
a
H
L
b
H
H
X
X
X
X
Q
Q
Gn  
Q
Gn  
Q
H0  
An  
An  
B0  
Q
Q
X
Q
A0  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

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SN74ALS166D 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALS166DRE4 TI

完全替代

 PARALLEL-LOAD 8-BIT SHIFT REGISTER
SN74ALS166DE4 TI

完全替代

 PARALLEL-LOAD 8-BIT SHIFT REGISTER
SN74ALS166DR TI

完全替代

 PARALLEL-LOAD 8-BIT SHIFT REGISTER

与SN74ALS166D相关器件

型号 品牌 获取价格 描述 数据表
SN74ALS166D3 TI

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 		IC IC,SHIFT REGISTER,ALS-TTL,SOP,16PIN,PLASTIC, Shift Register
SN74ALS166DBLE TI

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 		ALS SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, PLASTI
SN74ALS166DBR TI

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 		PARALLEL-LOAD 8-BIT SHIFT REGISTER
SN74ALS166DBRE4 TI

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 		PARALLEL-LOAD 8-BIT SHIFT REGISTER
SN74ALS166DBRG4 TI

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 		PARALLEL-LOAD 8-BIT SHIFT REGISTER
SN74ALS166DE4 TI

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 		PARALLEL-LOAD 8-BIT SHIFT REGISTER
SN74ALS166DG4 TI

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 		PARALLEL-LOAD 8-BIT SHIFT REGISTER
SN74ALS166DP3 TI

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 		IC IC,SHIFT REGISTER,ALS-TTL,SOP,16PIN,PLASTIC, Shift Register
SN74ALS166DR TI

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 		PARALLEL-LOAD 8-BIT SHIFT REGISTER
SN74ALS166DRE4 TI

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 		PARALLEL-LOAD 8-BIT SHIFT REGISTER

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