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SN74ALS166N PDF预览

SN74ALS166N

更新时间: 2024-09-29 23:06:15
品牌 Logo 应用领域
德州仪器 - TI 移位寄存器
页数 文件大小 规格书
11页 343K
描述
PARALLEL-LOAD 8-BIT SHIFT REGISTER

SN74ALS166N 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:1.57
Samacsys Description:Parallel-Load 8-Bit Serial Shift Registers其他特性:SISO OPERATION ALSO AVAILABLE
计数方向:RIGHT系列:ALS
JESD-30 代码:R-PDIP-T16JESD-609代码:e4
长度:19.305 mm负载电容(CL):50 pF
逻辑集成电路类型:PARALLEL IN SERIAL OUT最大频率@ Nom-Sup:45000000 Hz
最大I(ol):0.008 A位数:8
功能数量:1端子数量:16
最高工作温度:70 °C最低工作温度:
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
包装方法:TUBE峰值回流温度(摄氏度):NOT SPECIFIED
最大电源电流(ICC):24 mAProp。Delay @ Nom-Sup:13 ns
传播延迟(tpd):13 ns认证状态:Not Qualified
施密特触发器:No座面最大高度:5.08 mm
子类别:Shift Register最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.62 mm
最小 fmax:45 MHz

SN74ALS166N 数据手册

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SN74ALS166  
PARALLEL-LOAD 8-BIT SHIFT REGISTER  
SDAS156D – APRIL 1982 – REVISED AUGUST 2000  
D, DB, OR N PACKAGE  
(TOP VIEW)  
Synchronous Load  
Direct Overriding Clear  
Parallel-to-Serial Conversion  
SER  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
A
SH/LD  
Package Options Include Plastic  
Small-Outline (D) and Shrink Small-Outline  
(DB) Packages and Standard Plastic (N) DIP  
B
C
H
Q
H
D
G
description  
CLK INH  
CLK  
F
E
The SN74ALS166 parallel-load 8-bit shift register  
is compatible with most other TTL logic families.  
All inputs are buffered to lower the drive  
requirements. Input clamping diodes minimize  
switching transients and simplify system design.  
GND  
CLR  
These parallel-in or serial-in, serial-out registers have a complexity of 77 equivalent gates on the chip. They  
feature gated clocks (CLK and CLK INH) inputs and an overriding clear (CLR) input. The parallel-in or serial-in  
modes are established by the shift/load (SH/LD) input. When high, SH/LD enables the serial data (SER) input  
and couples the eight flip-flops for serial shifting with each clock pulse. When low, the parallel (broadside) data  
(A–H)inputsareenabledandsynchronousloadingoccursonthenextclockpulse. Duringparallelloading, serial  
data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of the clock pulse through a  
two-input positive-NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding  
either of the clock inputs high inhibits clocking; holding either low enables the other clock input. This allows the  
system clock to be free running and the register can be stopped on command with the clock input. CLK INH  
shouldbechangedtothehighlevelonlywhenCLKishigh. ThebufferedCLRoverridesallotherinputs, including  
CLK, and sets all flip-flops to zero.  
The SN74ALS166 is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
INTERNAL  
OUTPUTS  
OUTPUT  
PARALLEL  
Q
CLR  
SH/LD  
CLK  
CLK INH  
SER  
H
A . . . H  
Q
Q
B
A
L
X
X
L
X
L
L
L
L
H
X
L
X
X
X
H
L
X
L
L
L
H
H
H
H
H
X
Q
Q
Q
H0  
h
A0  
B0  
a . . . h  
a
H
L
b
H
H
X
X
X
X
Q
Q
Gn  
Q
Gn  
Q
H0  
An  
An  
B0  
Q
Q
X
Q
A0  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74ALS166N 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALS166NE4 TI

完全替代

PARALLEL-LOAD 8-BIT SHIFT REGISTER

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