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SN74ALS165NE4 PDF预览

SN74ALS165NE4

更新时间: 2024-11-06 05:24:55
品牌 Logo 应用领域
德州仪器 - TI 移位寄存器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
14页 559K
描述
PARALLEL-LOAD 8-BIT REGISTERS

SN74ALS165NE4 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP16,.3针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.51Is Samacsys:N
其他特性:CLOCK INHIBIT计数方向:RIGHT
系列:ALSJESD-30 代码:R-PDIP-T16
JESD-609代码:e4长度:19.305 mm
逻辑集成电路类型:PARALLEL IN SERIAL OUT位数:8
功能数量:1端子数量:16
最高工作温度:70 °C最低工作温度:
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
传播延迟(tpd):14 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:Shift Registers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:7.62 mm最小 fmax:45 MHz
Base Number Matches:1

SN74ALS165NE4 数据手册

 浏览型号SN74ALS165NE4的Datasheet PDF文件第2页浏览型号SN74ALS165NE4的Datasheet PDF文件第3页浏览型号SN74ALS165NE4的Datasheet PDF文件第4页浏览型号SN74ALS165NE4的Datasheet PDF文件第5页浏览型号SN74ALS165NE4的Datasheet PDF文件第6页浏览型号SN74ALS165NE4的Datasheet PDF文件第7页 
ꢀꢁꢂ ꢃ ꢄꢅ ꢀ ꢆꢇ ꢂ ꢈ ꢉꢀ ꢁꢊꢃ ꢄꢅ ꢀꢆ ꢇꢂ  
ꢋꢄꢌꢄ ꢅꢅ ꢍꢅ ꢎꢅ ꢏ ꢄꢐꢉꢑ ꢎꢒ ꢓꢔ ꢉꢌꢍ ꢕ ꢓꢀ ꢔꢍ ꢌ ꢀ  
SDAS157B − JUNE 1982 − REVISED DECEMBER 1994  
SN54ALS165 . . . J PACKAGE  
SN74ALS165 . . . D OR N PACKAGE  
(TOP VIEW)  
Complementary Outputs  
Direct Overriding Load (Data) Inputs  
Gated Clock Inputs  
SH/LD  
CLK  
E
V
CC  
CLK INH  
Parallel-to-Serial Data Conversion  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
D
C
B
A
F
G
H
Q
SER  
description  
H
GND  
Q
H
The ALS165 are parallel-load 8-bit serial shift  
registers that, when clocked, shift the data toward  
SN54ALS165 . . . FK PACKAGE  
(TOP VIEW)  
serial (Q and Q ) outputs. Parallel-in access to  
H
H
each stage is provided by eight individual direct  
data (AH) inputs that are enabled by a low level  
at the shift/load (SH/LD) input. The ALS165 have  
a clock-inhibit function and complemented serial  
outputs.  
3
2
1
20 19  
18  
E
F
D
4
5
6
7
8
Clocking is accomplished by a low-to-high  
transition of the clock (CLK) input while SH/LD is  
held high and the clock inhibit (CLK INH) input is  
held low. The functions of CLK and CLK INH are  
interchangeable. Since a low CLK and a  
low-to-high transition of CLK INH also  
accomplishes clocking, CLK INH should be  
changed to the high level only while CLK is high.  
Parallel loading is inhibited when SH/LD is held  
high. The parallel inputs to the register are  
enabled while SH/LD is low independently of the  
levels of the CLK, CLK INH, or serial (SER) inputs.  
17  
16  
15  
14  
C
NC  
G
NC  
B
H
A
9 10 11 12 13  
NC − No internal connection  
The SN54ALS165 is characterized for operation over the full military temperature range of 55°C to 125°C. The  
SN74ALS165 is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
FUNCTION  
CLK CLK INH  
SH/LD  
L
X
H
X
L
X
X
H
L
Parallel load  
No change  
No change  
H
H
H
H
Shift  
Shift  
Shift = content of each internal register shifts  
toward serial outputs. Data at SER is shifted  
into first register.  
ꢔꢤ  
Copyright 1994, Texas Instruments Incorporated  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

SN74ALS165NE4 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALS165N TI

完全替代

PARALLEL-LOAD 8-BIT REGISTERS
SNJ54ALS165J TI

完全替代

PARALLEL-LOAD 8-BIT REGISTERS

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SN74ALS166D TI

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SN74ALS166D3 TI

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SN74ALS166DBLE TI

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ALS SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, PLASTI
SN74ALS166DBR TI

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PARALLEL-LOAD 8-BIT SHIFT REGISTER
SN74ALS166DBRE4 TI

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PARALLEL-LOAD 8-BIT SHIFT REGISTER