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SN74ALS164AN PDF预览

SN74ALS164AN

更新时间: 2024-11-11 23:06:15
品牌 Logo 应用领域
德州仪器 - TI 移位寄存器触发器逻辑集成电路光电二极管输入元件PC
页数 文件大小 规格书
6页 97K
描述
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTER

SN74ALS164AN 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:DIP包装说明:DIP, DIP14,.3
针数:14Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:1.51Samacsys Confidence:
Samacsys Status:ReleasedSamacsys PartID:606828
Samacsys Pin Count:14Samacsys Part Category:Integrated Circuit
Samacsys Package Category:OtherSamacsys Footprint Name:DIP254P762X508-14
Samacsys Released Date:2017-01-12 12:59:53Is Samacsys:N
其他特性:AND-GATED SERIAL (A AND B) INPUTS计数方向:RIGHT
系列:ALSJESD-30 代码:R-PDIP-T14
JESD-609代码:e4长度:19.3 mm
负载电容(CL):50 pF逻辑集成电路类型:SERIAL IN PARALLEL OUT
最大频率@ Nom-Sup:50000000 Hz最大I(ol):0.008 A
位数:8功能数量:1
端子数量:14最高工作温度:70 °C
最低工作温度:输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:TUBE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):24 mAProp。Delay @ Nom-Sup:17 ns
传播延迟(tpd):17 ns认证状态:Not Qualified
施密特触发器:No座面最大高度:5.08 mm
子类别:Shift Registers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:6.35 mm
最小 fmax:50 MHzBase Number Matches:1

SN74ALS164AN 数据手册

 浏览型号SN74ALS164AN的Datasheet PDF文件第2页浏览型号SN74ALS164AN的Datasheet PDF文件第3页浏览型号SN74ALS164AN的Datasheet PDF文件第4页浏览型号SN74ALS164AN的Datasheet PDF文件第5页浏览型号SN74ALS164AN的Datasheet PDF文件第6页 
SN74ALS164A  
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTER  
SDAS159D – APRIL 1982 – REVISED DECEMBER 1994  
D OR N PACKAGE  
(TOP VIEW)  
AND-Gated (Enable/Disable) Serial Inputs  
Fully Buffered Clock and Serial Inputs  
Direct Clear  
Package Options Include Plastic  
Small-Outline (D) Packages and Standard  
Plastic (N) 300-mil DIPs  
A
B
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
Q
Q
Q
Q
CLR  
CLK  
H
G
F
Q
Q
Q
A
B
C
D
E
description  
Q
GND  
8
This 8-bit parallel-out serial shift register features  
AND-gated serial (A and B) inputs and an  
asynchronous clear (CLR) input. The gated serial  
inputs permit control over incoming data because a low at either input inhibits entry of the new data and resets  
the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input, which  
determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock is high or low,  
provided that the minimum setup-time requirements are met. Clocking occurs on the low-to-high-level transition  
of the clock (CLK) input. All inputs are diode clamped to minimize transmission-line effects.  
The SN74ALS164A is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
CLR  
L
CLK  
A
X
X
H
L
B
X
X
H
X
L
Q
Q
B
. . . Q  
A
H
X
L
L
L
L
H
Q
Q
Q
H0  
Q
Gn  
Q
Gn  
Q
Gn  
A0  
B0  
An  
An  
An  
H
H
L
L
Q
Q
Q
H
H
X
Q
, Q , Q = the level of Q , Q , or Q , respectively,  
A0 B0 H0  
A
B
H
before the indicated steady-state input conditions were  
established.  
H = high level (steady state), L = low level (steady state)  
X = irrelevant (any input, including transitions)  
= transition from low to high level  
Q
, Q = the level of Q or Q before the most recent  
An Gn A G  
transition of the clock; indicates a 1-bit shift.  
Copyright 1994, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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