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SN74AHC74DG4 PDF预览

SN74AHC74DG4

更新时间: 2024-11-06 20:58:15
品牌 Logo 应用领域
德州仪器 - TI 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
27页 1812K
描述
Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 14-SOIC -40 to 125

SN74AHC74DG4 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP14,.25
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.11
系列:AHC/VHC/H/U/VJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:8.65 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:75000000 Hz最大I(ol):0.008 A
湿度敏感等级:1位数:1
功能数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TUBE峰值回流温度(摄氏度):260
电源:2/5.5 VProp。Delay @ Nom-Sup:10.5 ns
传播延迟(tpd):17.5 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:3.9 mm最小 fmax:110 MHz
Base Number Matches:1

SN74AHC74DG4 数据手册

 浏览型号SN74AHC74DG4的Datasheet PDF文件第2页浏览型号SN74AHC74DG4的Datasheet PDF文件第3页浏览型号SN74AHC74DG4的Datasheet PDF文件第4页浏览型号SN74AHC74DG4的Datasheet PDF文件第5页浏览型号SN74AHC74DG4的Datasheet PDF文件第6页浏览型号SN74AHC74DG4的Datasheet PDF文件第7页 
SN54AHC74, SN74AHC74  
www.ti.com  
SCLS255K DECEMBER 1995REVISED DECEMBER 2013  
Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset  
Check for Samples: SN54AHC74, SN74AHC74  
1
FEATURES  
DESCRIPTION  
The ’AHC74 dual positive-edge-triggered devices are  
D-type flip-flops.  
Operating Range 2-V to 5.5-V VCC  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
A low level at the preset (PRE) or clear (CLR) inputs  
sets or resets the outputs, regardless of the levels of  
the other inputs. When PRE and CLR are inactive  
(high), data at the data (D) input meeting the setup  
time requirements is transferred to the outputs on the  
positive-going edge of the clock pulse. Clock  
triggering occurs at a voltage level and is not directly  
related to the rise time of the clock pulse. Following  
the hold-time interval, data at the D input can be  
changed without affecting the levels at the outputs.  
ESD Protection Exceeds JESD 22  
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
1000-V Charged-Device Model (C101)  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 1995–2013, Texas Instruments Incorporated  
 

SN74AHC74DG4 替代型号

型号 品牌 替代类型 描述 数据表
SN74AHC74DR TI

类似代替

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74AHC74DBR TI

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DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74AHC74D TI

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DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

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