SN74AHC74-EP

更新时间： 2024-11-05 11:58:43

品牌	Logo	应用领域
德州仪器 - TI		触发器
页数	文件大小	规格书
10页	452K
描述
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

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SN74AHC74-EP 数据手册

SN74AHC74-EP

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

WITH CLEAR AND PRESET

SCLS489 – JUNE 2003

D OR PW PACKAGE

(TOP VIEW)

Controlled Baseline

– One Assembly/Test Site, One Fabrication

Site

1CLR

2CLR

Extended Temperature Performance of

–55°C to 125°C

1CLK

1PRE

Enhanced Diminishing Manufacturing

Sources (DMS) Support

2CLK

2PRE

Enhanced Product-Change Notification

†

Qualification Pedigree

GND

EPIC (Enhanced-Performance Implanted

CMOS) Process

Operating Range 2-V to 5.5-V V

Latch-Up Performance Exceeds 250 mA Per

JESD 17

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

†

Component qualification in accordance with JEDEC and industry

standards to ensure reliable operation over an extended

temperature range. This includes, but is not limited to, Highly

Accelerated Stress Test (HAST) or biased 85/85, temperature

cycle, autoclave or unbiased HAST, electromigration, bond

intermetallic life, and mold compound life. Such qualification

testing should not be viewed as justifying use of this component

beyond specified performance and environmental limits.

description/ordering information

The SN74AHC74 dual positive-edge-triggered device is a D-type flip-flop.

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the

other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time

requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs

at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,

data at the D input can be changed without affecting the levels at the outputs.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

‡

PACKAGE

SOIC – D

Tape and reel

SN74AHC74MDREP

SN74AHC74MPWREP

AHC74MEP

AHC74EP

–55°C to 125°C

TSSOP – PW

‡

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...10

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与SN74AHC74-EP相关器件

型号	品牌	获取价格	描述	数据表
SN74AHC74MDREP	TI	获取价格	Enhanced Product Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset 14-S
SN74AHC74MPWREP	TI	获取价格	暂无描述
SN74AHC74N	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74AHC74NE4	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74AHC74NSR	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74AHC74NSRE4	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74AHC74PW	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74AHC74PWE4	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74AHC74PWG4	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74AHC74PWLE	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

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