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SN65MLVD082 PDF预览

SN65MLVD082

更新时间: 2024-11-26 22:29:03
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24页 237K
描述
8 CHANNEL HALF DUPLEX M LVDS LINE TRANSCEIVERS

SN65MLVD082 数据手册

 浏览型号SN65MLVD082的Datasheet PDF文件第2页浏览型号SN65MLVD082的Datasheet PDF文件第3页浏览型号SN65MLVD082的Datasheet PDF文件第4页浏览型号SN65MLVD082的Datasheet PDF文件第5页浏览型号SN65MLVD082的Datasheet PDF文件第6页浏览型号SN65MLVD082的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇꢈ ꢉꢈ  
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇꢈ ꢉꢊ  
www.ti.com  
SLLS581A − SEPTEMBER 2003 − REVISED SEPTEMBER 2003  
multipoint buses presenting loads as low as 30-and  
incorporates controlled transition times to allow for stubs  
off of the backbone transmission line.  
FEATURES  
D
Low-Voltage Differential 30-to 55-Line  
Drivers and Receivers for Signaling Rates  
(1)  
The M-LVDS standard defines two types of receivers,  
designated as Type-1 and Type-2. Type-1 receivers  
(SN65MLVD080) have thresholds centered about zero  
with 25 mV of hysteresis to prevent output oscillations with  
loss of input; Type-2 receivers (SN65MLVD082)  
implement a failsafe by using an offset threshold. In  
addition, the driver rise and fall times are between 1 and  
2.0 ns, complying with the M-LVDS standard to provide  
operation at 250 Mbps while also accommodating stubs on  
the bus. Receiver outputs are slew rate controlled to  
reduce EMI and crosstalk effects associated with large  
current surges. The M-LVDS standard allows for 32 nodes  
on the bus providing a high-speed replacement for RS-485  
where lower common-mode can be tolerated or when  
higher signaling rates are needed.  
Up to 250 Mbps; Clock Frequencies Up to 125  
MHz  
D
Meets or Exceeds the M-LVDS Standard  
TIA/EIA-899 for Multipoint Data Interchange  
D
D
Power Up/Down Glitch Free  
Controlled Driver Output Voltage Transition  
Times for Improved Signal Quality  
D
−1 V to 3.4 V Common-Mode Voltage Range  
Allows Data Transfer With 2 V of Ground  
Noise  
D
Bus Pins High Impedance When Driver  
Disabled or V  
1.5 V  
CC  
D
D
D
Independent Enables for each Driver  
Bus Pin ESD Protection Exceeds 8 kV  
Packaged in 64-Pin TSSOP (DGG)  
The driver logic inputs and the receiver logic outputs are  
on separate pins rather than tied together as in some  
transceiver designs. The drivers have separate enables  
(DE) and the receivers are enabled globally through (RE).  
This arrangement of separate logic inputs, logic outputs,  
and enable pins allows for a listen-while-talking operation.  
The devices are characterized for operation from −40°C to  
85°C.  
APPLICATIONS  
D
D
Parallel Multipoint Data and Clock  
Transmission Via Backplanes and Cables  
Low-Power High-Speed Short-Reach  
Alternative to TIA/EIA-485  
LOGIC DIAGRAM (POSITIVE LOGIC)  
SN65MLVD080, SN65MLVD082  
Channel 1  
1DE  
D
D
D
Cellular Base Stations  
Central-Office Switches  
Network Switches and Routers  
1A  
1D  
1B  
1R  
RE  
DESCRIPTION  
The SN65MLVD080 and SN65MLVD082 provide eight  
half-duplex transceivers for transmitting and receiving  
Multipoint-Low-Voltage Differential Signals in full  
compliance with the TIA/EIA-899 (M-LVDS) standard,  
which are optimized to operate at signaling rates up to 250  
Mbps. The driver outputs have been designed to support  
7
2DE − 8DE  
2A − 8A  
2B − 8B  
7
2D − 8D  
2R − 8R  
Channels 2 − 8  
7
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments  
semiconductor products and disclaimers thereto appears at the end of this data sheet.  
(1)  
The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second).  
ꢒꢖ ꢗ ꢇꢑ ꢌ ꢕꢔ ꢗꢁ ꢇ ꢎꢕꢎ ꢘꢙ ꢚꢛ ꢜ ꢝꢞ ꢟꢘꢛꢙ ꢘꢠ ꢡꢢ ꢜ ꢜ ꢣꢙꢟ ꢞꢠ ꢛꢚ ꢤꢢꢥ ꢦꢘꢡ ꢞꢟꢘ ꢛꢙ ꢧꢞ ꢟꢣꢨ ꢒꢜ ꢛꢧꢢ ꢡꢟꢠ  
ꢡ ꢛꢙ ꢚꢛꢜ ꢝ ꢟꢛ ꢠ ꢤꢣ ꢡ ꢘ ꢚꢘ ꢡ ꢞ ꢟꢘ ꢛꢙꢠ ꢤ ꢣꢜ ꢟꢩꢣ ꢟꢣ ꢜ ꢝꢠ ꢛꢚ ꢕꢣꢪ ꢞꢠ ꢔꢙꢠ ꢟꢜ ꢢꢝ ꢣꢙꢟ ꢠ ꢠꢟ ꢞꢙꢧ ꢞꢜ ꢧ ꢫ ꢞꢜ ꢜ ꢞ ꢙꢟꢬꢨ  
ꢒꢜ ꢛ ꢧꢢꢡ ꢟ ꢘꢛ ꢙ ꢤꢜ ꢛ ꢡ ꢣ ꢠ ꢠ ꢘꢙ ꢭ ꢧꢛ ꢣ ꢠ ꢙꢛꢟ ꢙꢣ ꢡꢣ ꢠꢠ ꢞꢜ ꢘꢦ ꢬ ꢘꢙꢡ ꢦꢢꢧ ꢣ ꢟꢣ ꢠꢟꢘ ꢙꢭ ꢛꢚ ꢞꢦ ꢦ ꢤꢞ ꢜ ꢞꢝ ꢣꢟꢣ ꢜ ꢠꢨ  
Copyright 2003, Texas Instruments Incorporated  

SN65MLVD082 替代型号

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