Datasheet > SN65LVELT22_10

SN65LVELT22_10

更新时间： 2024-11-24 11:55:11

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
11页	431K
描述
3.3 V Dual LVTTL to DIfferential LVPECL Translator

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SN65LVELT22_10 数据手册

SN65LVELT22

www.ti.com ............................................................................................................................................................................................ SLLS928–DECEMBER 2008

3.3 V Dual LVTTL to DIfferential LVPECL Translator

FEATURES

APPLICATIONS

•

Data and Clock Transmission Over Backplane

•

450 ps (typ) Propagation Delay

•

Signaling Level Conversion for Clock or Data

•

Operating Range: V_CC3.0 V to 3.8 with

GND = 0 V

•

<50 ps (max) Output to Output Skew

Built-in Temperature Compensation

Drop in Compatible to MC100LVELT22

DESCRIPTION

The SN65ELT22 is a dual LVTTL to differential LVPECL translator buffer. It operates on +3V supply and ground

only. The output is driven default high when the inputs are left floating or unused. The low output skew makes

the device the ideal solution for clock or data signal translation.

The SN65LVELT22 is housed in an industry standard SOIC-8 package and is also available in TSSOP-8

package option.

PINOUT ASSIGNMENT

GND

Table 1. Pin Description

FUNCTION

D₀, D₁

Q₀, Q₀, Q₁, Q₁

V_CC

TTL inputs

PECL/ECL outputs

Positive supply

Ground

GND

ORDERING INFORMATION⁽¹⁾

PART NUMBER

PART MARKING

SN65LVELT22

PACKAGE

SOIC

LEAD FINISH

NiPdAu

SN65LVELT22D

SN65LVELT22DGK

SOIC-TSSOP

NiPdAu

(1) Leaded device options not initially available. Contact TI sales representative for further details.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...11

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与SN65LVELT22_10相关器件

型号	品牌	获取价格	描述	数据表
SN65LVELT22D	TI	获取价格	3.3 V Dual LVTTL to DIfferential LVPECL Translator
SN65LVELT22DGK	TI	获取价格	3.3 V Dual LVTTL to DIfferential LVPECL Translator
SN65LVELT22DGKR	TI	获取价格	3.3 V Dual LVTTL to DIfferential LVPECL Translator
SN65LVELT22DR	TI	获取价格	3.3 V Dual LVTTL to DIfferential LVPECL Translator
SN65LVELT23	TI	获取价格	3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator
SN65LVELT23D	TI	获取价格	3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator
SN65LVELT23DGK	TI	获取价格	3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator
SN65LVELT23DGKR	TI	获取价格	3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator
SN65LVELT23DR	TI	获取价格	3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator
SN65LVEP11	TI	获取价格	2.5 V/3.3 V PECL/ECL 1:2 Fanout Buffer