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SN65LVELT22DR PDF预览

SN65LVELT22DR

更新时间: 2024-11-27 06:12:51
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器逻辑集成电路光电二极管PC
页数 文件大小 规格书
10页 417K
描述
3.3 V Dual LVTTL to DIfferential LVPECL Translator

SN65LVELT22DR 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:SOIC
包装说明:SOIC-8针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:12 weeks风险等级:1.21
Samacsys Confidence:Samacsys Status:Released
Samacsys PartID:606785Samacsys Pin Count:8
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Other
Samacsys Footprint Name:SOIC127P600X175-8NSamacsys Released Date:2017-01-12 12:59:53
Is Samacsys:N系列:65EL
输入调节:STANDARDJESD-30 代码:R-PDSO-G8
JESD-609代码:e4长度:4.9 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:1
功能数量:2反相输出次数:
端子数量:8实输出次数:2
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TR峰值回流温度(摄氏度):260
传播延迟(tpd):0.55 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.1 ns座面最大高度:1.75 mm
最大供电电压 (Vsup):5.7 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mmBase Number Matches:1

SN65LVELT22DR 数据手册

 浏览型号SN65LVELT22DR的Datasheet PDF文件第2页浏览型号SN65LVELT22DR的Datasheet PDF文件第3页浏览型号SN65LVELT22DR的Datasheet PDF文件第4页浏览型号SN65LVELT22DR的Datasheet PDF文件第5页浏览型号SN65LVELT22DR的Datasheet PDF文件第6页浏览型号SN65LVELT22DR的Datasheet PDF文件第7页 
SN65LVELT22  
www.ti.com ............................................................................................................................................................................................ SLLS928DECEMBER 2008  
3.3 V Dual LVTTL to DIfferential LVPECL Translator  
1
FEATURES  
APPLICATIONS  
Data and Clock Transmission Over Backplane  
450 ps (typ) Propagation Delay  
Signaling Level Conversion for Clock or Data  
Operating Range: VCC 3.0 V to 3.8 with  
GND = 0 V  
<50 ps (max) Output to Output Skew  
Built-in Temperature Compensation  
Drop in Compatible to MC100LVELT22  
DESCRIPTION  
The SN65ELT22 is a dual LVTTL to differential LVPECL translator buffer. It operates on +3V supply and ground  
only. The output is driven default high when the inputs are left floating or unused. The low output skew makes  
the device the ideal solution for clock or data signal translation.  
The SN65LVELT22 is housed in an industry standard SOIC-8 package and is also available in TSSOP-8  
package option.  
PINOUT ASSIGNMENT  
1
2
8
7
V
CC  
Q
Q
0
D
D
0
0
1
6
5
Q
Q
1
4
GND  
1
Table 1. Pin Description  
PIN  
FUNCTION  
D0, D1  
Q0, Q0, Q1, Q1  
VCC  
TTL inputs  
PECL/ECL outputs  
Positive supply  
Ground  
GND  
ORDERING INFORMATION(1)  
PART NUMBER  
PART MARKING  
SN65LVELT22  
SN65LVELT22  
PACKAGE  
SOIC  
LEAD FINISH  
NiPdAu  
SN65LVELT22D  
SN65LVELT22DGK  
SOIC-TSSOP  
NiPdAu  
(1) Leaded device options not initially available. Contact TI sales representative for further details.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2008, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

SN65LVELT22DR 替代型号

型号 品牌 替代类型 描述 数据表
SN65LVELT22DGK TI

完全替代

3.3 V Dual LVTTL to DIfferential LVPECL Translator
SN65LVELT22D TI

完全替代

3.3 V Dual LVTTL to DIfferential LVPECL Translator

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