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SN65LVEP11DGK PDF预览

SN65LVEP11DGK

更新时间: 2024-11-24 06:12:51
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器逻辑集成电路光电二极管PC
页数 文件大小 规格书
10页 273K
描述
2.5 V/3.3 V PECL/ECL 1:2 Fanout Buffer

SN65LVEP11DGK 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:MSOP
包装说明:VSSOP-8针数:8
Reach Compliance Code:compliantECCN代码:5A991.B.1
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:1.21Samacsys Confidence:
Samacsys Status:ReleasedSamacsys PartID:606790
Samacsys Pin Count:8Samacsys Part Category:Integrated Circuit
Samacsys Package Category:OtherSamacsys Footprint Name:SOP65P490X110-8N
Samacsys Released Date:2017-01-12 12:59:53Is Samacsys:N
其他特性:NECL MODE: VCC = 0V WITH VEE = -2.375V TO -3.8V系列:65LVEP
输入调节:DIFFERENTIALJESD-30 代码:R-PDSO-G8
JESD-609代码:e4长度:3 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:8实输出次数:2
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP8,.19封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TUBE
峰值回流温度(摄氏度):260电源:+-2.5/+-3.3 V
最大电源电流(ICC):45 mAProp。Delay @ Nom-Sup:0.3 ns
传播延迟(tpd):0.3 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.025 ns座面最大高度:1.1 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.8 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3 mm
Base Number Matches:1

SN65LVEP11DGK 数据手册

 浏览型号SN65LVEP11DGK的Datasheet PDF文件第2页浏览型号SN65LVEP11DGK的Datasheet PDF文件第3页浏览型号SN65LVEP11DGK的Datasheet PDF文件第4页浏览型号SN65LVEP11DGK的Datasheet PDF文件第5页浏览型号SN65LVEP11DGK的Datasheet PDF文件第6页浏览型号SN65LVEP11DGK的Datasheet PDF文件第7页 
SN65LVEP11  
www.ti.com ........................................................................................................................................ SLLS930ANOVEMBER 2008REVISED DECEMBER 2008  
2.5 V/3.3 V PECL/ECL 1:2 Fanout Buffer  
1
FEATURES  
1:2 PECL/ECL Fanout Buffer  
PINOUT ASSIGNMENT  
Operating Range  
PECL: VCC = 2.375 V to 3.8V With VEE = 0 V  
+
Q0  
VCC  
1
8
7
NECL: VCC = 0 V With VEE = –2.375V to  
–3.8 V  
Open Input Default State  
Q0  
2
D
Support for Clock Frequencies > 3.0 GHz  
240 ps Typical Propagation Delay  
+
Q1  
3
4
6
5
D
Deterministic Output Value for Open Input  
Conditions  
Q1  
VEE  
Q Output Will Default Low When Input Open or  
at VEE  
Built-in Temperature Compensation  
Table 1. PIN DESCRIPTION  
Drop in Compatible to MC10LVEP11,  
MC100LVEP11  
PIN  
FUNCTION  
D, D  
PECL/ECL data inputs  
PECL/ECL outputs  
Positive supply  
LVDS Input Compatible  
Q0, Q0, Q1, Q1  
DESCRIPTION  
VCC  
VEE  
Negative supply  
The SN65LVEP11 is a differential 1:2 PECL/ECL  
fanout buffer. The device includes circuitry to  
maintain known logic levels when the inputs are in an  
open condition. Single-ended clock input operation is  
limited to VCC 3 V in PECL mode, or VEE 3 V in  
NECL mode. The device is housed in an  
industry-standard SOIC-8 package and is also  
available in TSSOP-8 package option.  
ORDERING INFORMATION(1)  
PART NUMBER  
SN65LVEP11D  
PART MARKING  
PACKAGE  
LEAD FINISH  
SN65LVEP11  
SN65LVEP11  
SOIC  
NiPdAu  
NiPdAu  
SN65LVEP11DGK  
SOIC-TSSOP  
(1) Leaded device option not initially available; contact TI sales representative for further information.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2008, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

SN65LVEP11DGK 替代型号

型号 品牌 替代类型 描述 数据表
SN65LVEP11DGKR TI

完全替代

2.5 V/3.3 V PECL/ECL 1:2 Fanout Buffer
MC100LVEP11DTR2G ONSEMI

类似代替

2.5V / 3.3V ECL 1:2 Differential Fanout Buffer
MC100LVEP11DR2G ONSEMI

类似代替

2.5V / 3.3V ECL 1:2 Differential Fanout Buffer

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