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SN65LVELT23DR PDF预览

SN65LVELT23DR

更新时间: 2024-11-24 06:12:51
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器逻辑集成电路光电二极管PC
页数 文件大小 规格书
10页 263K
描述
3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator

SN65LVELT23DR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:GREEN, PLASTIC, MS-012AA, SOIC-8针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.38
Samacsys Confidence:Samacsys Status:Released
Samacsys PartID:606789Samacsys Pin Count:8
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Other
Samacsys Footprint Name:SOIC127P600X175-8NSamacsys Released Date:2017-01-12 12:59:53
Is Samacsys:N系列:65LVEL
输入调节:STANDARDJESD-30 代码:R-PDSO-G8
JESD-609代码:e4长度:4.9 mm
负载电容(CL):20 pF逻辑集成电路类型:LOW SKEW CLOCK DRIVER
最大I(ol):0.024 A湿度敏感等级:1
功能数量:2反相输出次数:
端子数量:8实输出次数:2
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TR峰值回流温度(摄氏度):260
Prop。Delay @ Nom-Sup:2.2 ns传播延迟(tpd):2.5 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.18 ns
座面最大高度:1.75 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm
最小 fmax:180 MHzBase Number Matches:1

SN65LVELT23DR 数据手册

 浏览型号SN65LVELT23DR的Datasheet PDF文件第2页浏览型号SN65LVELT23DR的Datasheet PDF文件第3页浏览型号SN65LVELT23DR的Datasheet PDF文件第4页浏览型号SN65LVELT23DR的Datasheet PDF文件第5页浏览型号SN65LVELT23DR的Datasheet PDF文件第6页浏览型号SN65LVELT23DR的Datasheet PDF文件第7页 
SN65LVELT23  
www.ti.com......................................................................................................................................................... SLLS929AJUNE 2009REVISED AUGUST 2009  
3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator  
1
FEATURES  
PINOUT ASSIGNMENT  
Dual 3.3-V Differential LVPECL/LVDS to LVTTL  
Buffer Translator  
24-mA LVTTL Ouputs  
Operating Range  
V
D0  
1
8
7
CC  
PECL VCC = 3 V to 3.6 V With  
GND = 0 V  
Q0  
2
D0  
LVPECL  
LVTTL  
Support for Clock Frequencies to >180 MHz  
2-ns Typical Propagation Delay  
Q1  
3
6
D1  
Internal Input Pullup and Pulldown Resistors  
Built-in Temperature Compensation  
Drop-In Compatible to MC100LVELT23  
GND  
4
5
D1  
APPLICATIONS  
Table 1. PIN DESCRIPTION  
Data and Clock Transmission Over Backplane  
Signaling Level Conversion for Clock or Data  
PIN  
FUNCTION  
PECL inputs  
D0, D0, D1, D1  
Q0, Q1  
TTL outputs  
DESCRIPTION  
VCC  
Positive supply  
Ground  
The  
SN65LVELT23  
is  
a
low-power  
dual  
GND  
LVPECL/LVDS to LVTTL translator device. The  
device includes circuitry to maintain inputs at VCC/2  
when left open. The SN65LVELT23 is housed in an  
industry-standard SOIC-8 package and is also  
available in a TSSOP-8 option.  
ORDERING INFORMATION(1)  
PART NUMBER  
SN65LVELT23D  
SN65LVELT23DGK  
PART MARKING  
PACKAGE  
LEAD FINISH  
NiPdAu  
LVEL23  
SIMI  
SOIC  
MSOP  
NiPdAu  
(1) Devices with lead (Pb)-bearing terminals not initially available; contact TI sales representative for further information.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2009, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

SN65LVELT23DR 替代型号

型号 品牌 替代类型 描述 数据表
SN65LVELT23DGKR TI

完全替代

3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator
SN65LVELT23D TI

完全替代

3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator

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