Datasheet > SN65LVDTS33D

SN65LVDTS33D

更新时间： 2024-11-24 05:18:07

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德州仪器 - TI		/
页数	文件大小	规格书
23页	530K
描述
HIGH-SPEED DIFFERENTIAL RECEIVERS

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SN65LVDTS33D 技术参数

生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP, SOP16,.25	针数：	16
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.83
差分输出：	NO	输入特性：	DIFFERENTIAL SCHMITT TRIGGER
接口集成电路类型：	LINE RECEIVER	接口标准：	EIA-644; TIA-644
JESD-30 代码：	R-PDSO-G16	长度：	9.9 mm
功能数量：	4	端子数量：	16
最高工作温度：	85 °C	最低工作温度：	-40 °C
最大输出低电流：	0.004 A	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP16,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
电源：	3.3 V	认证状态：	Not Qualified
最大接收延迟：	6 ns	接收器位数：	4
座面最大高度：	1.75 mm	子类别：	Line Driver or Receivers
最大压摆率：	23 mA	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	BICMOS
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
宽度：	3.9 mm	Base Number Matches：	1

SN65LVDTS33D 数据手册

SN65LVDS33, SN65LVDT33

SN65LVDS34, SN65LVDT34

www.ti.com

SLLS490B–MARCH 2001–REVISED NOVEMBER 2004

HIGH-SPEED DIFFERENTIAL RECEIVERS

The high-speed switching of LVDS signals usually

necessitates the use of a line impedance matching

resistor at the receiving-end of the cable or

transmission media. The SN65LVDT series of

receivers eliminates this external resistor by

integrating it with the receiver. The nonterminated

SN65LVDS series is also available for multidrop or

other termination circuits.

FEATURES

•

400-Mbps Signaling Rate⁽¹⁾and 200-Mxfr/s

Data Transfer Rate

•

Operates With a Single 3.3-V Supply

-4 V to 5 V Common-Mode Input Voltage

Range

•

Differential Input Thresholds <±50 mV With 50

mV of Hysteresis Over Entire Common-Mode

Input Voltage Range

SN65LVDS33D, SN65LVDT33D

SN65LVDS33PW, SN65LVDT33PW

Integrated 110-Ω Line Termination Resistors

D OR PW PACKAGE

logic diagram (positive logic)

On LVDT Products

(TOP VIEW)

•

TSSOP Packaging (33 Only)

Complies With TIA/EIA-644 (LVDS)

SN65LVDT33 ONLY

Active Failsafe Assures a High-Level Output

With No Input

•

Bus-Pin ESD Protection Exceeds 15 kV HBM

Input Remains High-Impedance on Power

Down

11 3Y

GND

•

TTL Inputs Are 5 V Tolerant

Pin-Compatible With the AM26LS32,

SN65LVDS32B, µA9637, SN65LVDS9637B

(1)

The signalling rate of a line, is the number of voltage transitions

that are made per second expressed in the units bps (bits per

second).

DESCRIPTION

SN65LVDS34D, SN65LVDT34D

This family of four LVDS data line receivers offers the

widest common-mode input voltage range in the

industry. These receivers provide an input voltage

range specification compatible with a 5-V PECL

signal as well as an overall increased ground-noise

tolerance. They are in industry standard footprints

with integrated termination as an option.

D PACKAGE

(TOP VIEW)

logic diagram (positive logic)

SN65LVDT34 ONLY

GND

Precise control of the differential input voltage

thresholds allows for inclusion of 50 mV of input

voltage hysteresis to improve noise rejection on

slowly changing input signals. The input thresholds

are still no more than ±50 mV over the full input

common-mode voltage range.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...23

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与SN65LVDTS33D相关器件

型号	品牌	获取价格	描述	数据表
SN65LVEL11	TI	获取价格	3.3 V ECL 1:2 Fanout Buffer
SN65LVEL11_09	TI	获取价格	3.3 V ECL 1:2 Fanout Buffer
SN65LVEL11_10	TI	获取价格	3.3 V ECL 1:2 Fanout Buffer
SN65LVEL11_101	TI	获取价格	3.3 V ECL 1:2 Fanout Buffer
SN65LVEL11D	TI	获取价格	3.3 V ECL 1:2 Fanout Buffer
SN65LVEL11DGK	TI	获取价格	3.3 V ECL 1:2 Fanout Buffer
SN65LVEL11DGKR	TI	获取价格	3.3 V ECL 1:2 Fanout Buffer
SN65LVEL11DR	TI	获取价格	3.3 V ECL 1:2 Fanout Buffer
SN65LVELT22	TI	获取价格	3.3 V Dual LVTTL to DIfferential LVPECL Translator
SN65LVELT22_10	TI	获取价格	3.3 V Dual LVTTL to DIfferential LVPECL Translator

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