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SN65LVDS34DG4 PDF预览

SN65LVDS34DG4

更新时间： 2024-11-18 05:25:03
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德州仪器 - TI /
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23页 530K
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HIGH-SPEED DIFFERENTIAL RECEIVERS

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SN65LVDS34DG4 数据手册

 浏览型号SN65LVDS34DG4的Datasheet PDF文件第2页浏览型号SN65LVDS34DG4的Datasheet PDF文件第3页浏览型号SN65LVDS34DG4的Datasheet PDF文件第4页浏览型号SN65LVDS34DG4的Datasheet PDF文件第5页浏览型号SN65LVDS34DG4的Datasheet PDF文件第6页浏览型号SN65LVDS34DG4的Datasheet PDF文件第7页 
SN65LVDS33, SN65LVDT33  
SN65LVDS34, SN65LVDT34  
www.ti.com  
SLLS490B–MARCH 2001–REVISED NOVEMBER 2004  
HIGH-SPEED DIFFERENTIAL RECEIVERS  
The high-speed switching of LVDS signals usually  
necessitates the use of a line impedance matching  
resistor at the receiving-end of the cable or  
transmission media. The SN65LVDT series of  
receivers eliminates this external resistor by  
integrating it with the receiver. The nonterminated  
SN65LVDS series is also available for multidrop or  
other termination circuits.  
FEATURES  
•
400-Mbps Signaling Rate(1) and 200-Mxfr/s  
Data Transfer Rate  
•
•
Operates With a Single 3.3-V Supply  
-4 V to 5 V Common-Mode Input Voltage  
Range  
•
•
Differential Input Thresholds <±50 mV With 50  
mV of Hysteresis Over Entire Common-Mode  
Input Voltage Range  
SN65LVDS33D, SN65LVDT33D  
SN65LVDS33PW, SN65LVDT33PW  
Integrated 110-Ω Line Termination Resistors  
D OR PW PACKAGE  
logic diagram (positive logic)  
On LVDT Products  
(TOP VIEW)  
•
•
•
TSSOP Packaging (33 Only)  
G
1B  
1A  
1Y  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
Complies With TIA/EIA-644 (LVDS)  
G
4B  
4A  
4Y  
G
SN65LVDT33 ONLY  
Active Failsafe Assures a High-Level Output  
With No Input  
1A  
1B  
1Y  
G
2Y  
•
•
Bus-Pin ESD Protection Exceeds 15 kV HBM  
Input Remains High-Impedance on Power  
Down  
2A  
11 3Y  
2A  
2B  
10  
9
2B  
GND  
3A  
3B  
2Y  
3Y  
4Y  
•
•
TTL Inputs Are 5 V Tolerant  
Pin-Compatible With the AM26LS32,  
3A  
3B  
4A  
4B  
SN65LVDS32B, µA9637, SN65LVDS9637B  
(1)  
The signalling rate of a line, is the number of voltage transitions  
that are made per second expressed in the units bps (bits per  
second).  
DESCRIPTION  
SN65LVDS34D, SN65LVDT34D  
This family of four LVDS data line receivers offers the  
widest common-mode input voltage range in the  
industry. These receivers provide an input voltage  
range specification compatible with a 5-V PECL  
signal as well as an overall increased ground-noise  
tolerance. They are in industry standard footprints  
with integrated termination as an option.  
D PACKAGE  
(TOP VIEW)  
logic diagram (positive logic)  
V
1A  
1B  
2A  
2B  
1
2
3
4
8
7
6
5
CC  
1A  
1Y  
2Y  
1Y  
1B  
SN65LVDT34 ONLY  
GND  
Precise control of the differential input voltage  
thresholds allows for inclusion of 50 mV of input  
voltage hysteresis to improve noise rejection on  
slowly changing input signals. The input thresholds  
are still no more than ±50 mV over the full input  
common-mode voltage range.  
2A  
2Y  
2B  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2001–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...23

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SN65LVDS34DG4 替代型号

型号 品牌 替代类型 描述 数据表
DS90LV028ATM/NOPB TI

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SN65LVDS9637D TI

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