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SN65LVDS388 PDF预览

SN65LVDS388

更新时间： 2024-11-01 23:03:07
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德州仪器 - TI /
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15页 207K
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HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

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SN65LVDS388 数据手册

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SN65LVDS386, SN65LVDT386, SN75LVDS386, SN75LVDT386  
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388  
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS  
SLLS394A – SEPTEMBER 1999 – REVISED DECEMBER 1999  
SN65LVDS388, SN75LVDS388  
SN65LVDT388, SN75LVDT388  
DBT PACKAGE  
SN65LVDS386, SN75LVDS386  
SN65LVDT386, SN75LVDT386  
DGG PACKAGE  
Eight (‘388) or Sixteen (‘386) Line Receivers  
Meet or Exceed the Requirements of ANSI  
TIA/EIA-644 Standard  
(TOP VIEW)  
(TOP VIEW)  
Integrated 110-Ω Line Termination  
Resistors on LVDT Products  
1
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
A1A  
A1B  
A2A  
A2B  
NC  
B1A  
B1B  
B2A  
B2B  
NC  
C1A  
C1B  
C2A  
C2B  
NC  
D1A  
D1B  
D2A  
D2B  
GND  
1
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
A1A  
A1B  
A2A  
A2B  
A3A  
A3B  
A4A  
A4B  
B1A  
B1B  
B2A  
B2B  
B3A  
B3B  
B4A  
B4B  
C1A  
C1B  
C2A  
C2B  
C3A  
C3B  
C4A  
C4B  
D1A  
D1B  
D2A  
D2B  
D3A  
D3B  
D4A  
D4B  
GND  
†
Designed for Signaling Rates Up To  
630 Mbps  
2
V
2
V
CC  
CC  
3
ENA  
A1Y  
A2Y  
ENB  
B1Y  
B2Y  
GND  
3
V
CC  
4
SN65 Version’s Bus-Terminal ESD Exceeds  
15 kV  
4
GND  
ENA  
A1Y  
A2Y  
A3Y  
A4Y  
ENB  
B1Y  
B2Y  
B3Y  
B4Y  
GND  
5
5
6
6
Operates From a Single 3.3-V Supply  
7
7
Typical Propagation Delay Time of 2.6 ns  
8
8
Output Skew 100 ps (Typ)  
Part-To-Part Skew is Less Than 1 ns  
9
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
V
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
CC  
LVTTL Levels are 5-V Tolerant  
Open-Circuit Fail Safe  
GND  
C1Y  
C2Y  
ENC  
D1Y  
D2Y  
END  
Flow-Through Pin Out  
Packaged in Thin Shrink Small-Outline  
Package With 20-mil Terminal Pitch  
V
V
CC  
CC  
description  
V
CC  
GND  
C1Y  
C2Y  
C3Y  
C4Y  
ENC  
D1Y  
D2Y  
D3Y  
D4Y  
END  
GND  
GND  
The ‘LVDS388 and ‘LVDT388 (T designates  
integrated termination) are eight and the  
‘LVDS386 and ‘LVDT386 sixteen differential line  
receivers respectively that implement the electri-  
cal characteristics of low-voltage differential  
signaling (LVDS). This signaling technique lowers  
the output voltage levels of 5-V differential  
standard levels (such as EIA/TIA-422B) to reduce  
the power, increase the switching speeds, and  
allow operation with a 3-V supply rail. Any of the  
eight or sixteen differential receivers will provide  
a valid logical output state with a ±100 mV  
differential input voltage within the input common-  
mode voltage range. The input common-mode  
voltage range allows 1 V of ground potential  
difference between two LVDS nodes. Additionally,  
the high-speed switching of LVDS signals almost  
always require the use of a line impedance  
matching resistor at the receiving end of the cable  
or transmission media. The LVDT products  
eliminate this external resistor by integrating it  
with the receiver.  
V
V
CC  
CC  
GND  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
†
Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...15

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