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SN65LVDS352PWRG4 PDF预览

SN65LVDS352PWRG4

更新时间： 2024-11-21 21:19:39
品牌 Logo 应用领域
德州仪器 - TI 信息通信管理光电二极管接口集成电路
页数 文件大小 规格书
22页 402K
描述
QUAD LINE RECEIVER, PDSO24, GREEN, PLASTIC, TSSOP-24

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SN65LVDS352PWRG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP24,.25针数：24
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.65
差分输出：NO输入特性：DIFFERENTIAL SCHMITT TRIGGER
接口集成电路类型：LINE RECEIVER接口标准：EIA-644-A; TIA-644-A
JESD-30 代码：R-PDSO-G24长度：7.8 mm
功能数量：4端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
最大输出低电流：0.004 A封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP24,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
认证状态：Not Qualified最大接收延迟：6 ns
接收器位数：4座面最大高度：1.2 mm
子类别：Line Driver or Receivers最大压摆率：20 mA
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mmBase Number Matches：1

SN65LVDS352PWRG4 数据手册

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SN65LVDS348 , SN65LVDT348  
SN65LVDS352, SN65LVDT352  
www.ti.com  
SLLS523E–FEBRUARY 2002–REVISED MAY 2004  
QUAD HIGH-SPEED DIFFERENTIAL RECEIVERS  
FEATURES  
DESCRIPTION  
•
•
•
Meets or Exceeds the Requirements of ANSI  
TIA/EIA-644A Standard  
The SN65LVDS348, SN65LVDT348, SN65LVDS352,  
and SN65LVDT352 are high-speed, quadruple  
differential receivers with a wide common-mode input  
voltage range. This allows receipt of TIA/EIA-644  
signals with up to 3-V of ground noise or a variety of  
differential and single-ended logic levels. The '348 is  
in a 16-pin package to match the industry-standard  
footprint of the DS90LV048. The '352 adds two  
additional VCC and GND pins in a 24-pin package to  
provide higher data transfer rates with multiple  
Single-Channel Signaling Rates up to  
560 Mbps  
-4 V to 5 V Common-Mode Input Voltage  
Range  
•
•
Flow-Through Architecture  
Active Failsafe Assures a High-level Output  
When an Input Signal Is not Present  
receivers in operation. All offer  
a flow-through  
•
SN65LVDS348 Provides a Wide Common-  
Mode Range Replacement for the  
SN65LVDS048A or the DS90LV048A  
architecture with all inputs on one side and outputs  
on the other to ease board layout and reduce  
crosstalk between receivers. LVDT versions of both  
integrate a 110-Ω line termination resistor.  
APPLICATIONS  
These receivers also provide 3x the standard's  
minimum common-mode noise voltage tolerance. The  
-4 V to 5 V common-mode range allows usage in  
harsh operating environments or accepts LVPECL,  
PECL, LVECL, ECL, CMOS, and LVCMOS levels  
without level shifting circuitry. See the Application  
Information Section for more details on the  
ECL/PECL to LVDS interface.  
•
Logic Level Translator  
•
Point-to-Point Baseband Data Transmission  
Over 100-Ω Media  
•
•
•
ECL/PECL-to-LVTTL Conversion  
Wireless Base Stations  
Central Office or PABX Switches  
DATA TRANSFER RATE  
vs  
FREE-AIR TEMPERATURE  
550  
Timer  
SN65LVDS352PW  
500  
LVDT Device  
Only  
450  
400  
SN65LVDS348PW  
350  
(One of Four Shown)  
300  
15  
2
-1 prbs NRZ, V = 0.4 V  
ID  
= 1.2 V, C = 5.5 pF, 40% Open Eye  
L
250  
200  
V
IC  
4 Receivers Switching, Input Jitter < 45 ps  
-60  
-40  
-20  
0
20  
40  
60  
80  
100  
T - Free-Air Temperature - °C  
A
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2002–2004, Texas Instruments Incorporated  
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SN65LVDS352PWRG4 替代型号

型号 品牌 替代类型 描述 数据表
SN65LVDT352PWR TI

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 具有 –4V 至 5V 共模范围的四路接收器 | PW | 24 | -40 to 85
SN65LVDS352PW TI

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SN65LVDT352PW TI

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