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SN65LVDS388DBTR PDF预览

SN65LVDS388DBTR

更新时间： 2024-11-02 09:17:07
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
14页 204K
描述
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

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SN65LVDS388DBTR 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP38,.25,20
针数：38Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：5.17
差分输出：NO驱动器位数：8
输入特性：DIFFERENTIAL接口集成电路类型：LINE RECEIVER
接口标准：EIA-644; TIA-644JESD-30 代码：R-PDSO-G38
长度：9.7 mm功能数量：8
端子数量：38最高工作温度：85 °C
最低工作温度：-40 °C最大输出低电流：0.008 A
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP38,.25,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V认证状态：Not Qualified
最大接收延迟：4 ns接收器位数：8
座面最大高度：1.2 mm子类别：Line Driver or Receivers
最大压摆率：70 mA最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4.4 mm
Base Number Matches：1

SN65LVDS388DBTR 数据手册

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SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388  
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS  
SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001  
Eight Line Receivers Meet or Exceed the  
Requirements of ANSI TIA/EIA-644  
Standard  
NOT RECOMMENDED FOR NEW DESIGNS  
For Replacement Use ’LVDx388A  
Integrated 110-Ω Line Termination  
Resistors on LVDT Products  
’LVDS388, ’LVDT388  
DBT PACKAGE  
(TOP VIEW)  
†
Designed for Signaling Rates Up To  
630 Mbps  
1
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
A1A  
A1B  
A2A  
A2B  
NC  
B1A  
B1B  
B2A  
B2B  
NC  
C1A  
C1B  
C2A  
C2B  
NC  
D1A  
D1B  
D2A  
D2B  
GND  
SN65 Version’s Bus-Terminal ESD Exceeds  
15 kV  
2
V
CC  
3
ENA  
A1Y  
A2Y  
ENB  
B1Y  
B2Y  
GND  
Operates From a Single 3.3-V Supply  
Propagation Delay Time of 2.6 ns (Typ)  
4
5
6
Output Skew 100 ps (Typ)  
Part-To-Part Skew Is Less Than 1 ns  
7
8
LVTTL Levels Are 5-V Tolerant  
Open-Circuit Fail Safe  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
V
CC  
Flow-Through Pin Out  
GND  
C1Y  
C2Y  
ENC  
D1Y  
D2Y  
END  
Packaged in Thin Shrink Small-Outline  
Package With 20-mil Terminal Pitch  
description  
The ‘LVDS388 and ‘LVDT388 (T designates  
integrated termination) are eight differential line  
receivers that implement the electrical character-  
istics of low-voltage differential signaling (LVDS).  
Thissignalingtechniquelowerstheoutputvoltage  
levels of 5-V differential standard levels (such as  
EIA/TIA-422B) to reduce the power, increase the  
switching speeds, and allow operation with a 3-V  
supply rail. Any of the eight differential receivers  
will provide a valid logical output state with a  
+100-mV differential input voltage within the input  
common-mode voltage range. The input  
common-mode voltage range allows 1 V of  
ground potential difference between two LVDS  
nodes. Additionally, the high-speed switching of  
LVDS signals always require the use of a line  
impedance matching resistor at the receiving end  
of the cable or transmission media. The LVDT  
product eliminates this external resistor by  
integrating it with the receiver.  
V
CC  
GND  
logic diagram (positive logic)  
’LVDx388  
’LVDT388 ONLY  
1A  
1Y  
1B  
EN  
2A  
2Y  
2B  
(1/4 of ’LVDx388 shown)  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
†
Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)  
Copyright 2001, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...14

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