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SN65LV1224A PDF预览

SN65LV1224A

更新时间: 2024-11-20 21:54:07
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
22页 314K
描述
10-MHz TO 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER

SN65LV1224A 数据手册

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SN65LV1023A/SN65LV1224A  
10-MHz TO 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER  
SLLS570A – JUNE 2003 – REVISED JUNE 2003  
D
100-Mbps to 660-Mbps Serial LVDS Data  
Payload Bandwidth at 10-MHz to 66-MHz  
System Clock  
D
D
D
D
Lock Indicator  
No External Components Required for PLL  
Low-Cost 28-Pin SSOP Package  
Industrial Temperature Qualified,  
D
D
D
Pin-Compatible Superset of NSM  
DS92LV1023/DS92LV1224  
T = 40°C to 85°C  
A
Chipset (Serializer/Deserializer) Power  
Consumption <450 mW (Typ) at 66 MHz  
D
Programmable Edge Trigger on Clock  
D
Flow-Through Pinout for Easy PCB Layout  
Synchronization Mode for Faster Lock  
SN65LV1023A  
Serializer  
SN65LV1224A  
Deserializer  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
SYNC1  
SYNC2  
DV  
DV  
AV  
AGND  
PWRDN  
AGND  
AGND  
RCLK_R/F  
REFCLK  
R
R
R
R
R
CC  
CC  
CC  
OUT0  
OUT1  
OUT2  
OUT3  
OUT4  
2
2
3
3
D
D
D
D
D
D
D
D
D
D
IN0  
IN1  
IN2  
IN3  
IN4  
IN5  
IN6  
IN7  
IN8  
IN9  
4
4
AV  
CC  
5
5
R +  
I
6
6
R –  
DV  
DGND  
DV  
I
CC  
7
7
D +  
PWRDN  
REN  
RCLK  
LOCK  
O
8
8
D –  
O
CC  
9
9
AGND  
DEN  
AGND  
DGND  
10  
11  
12  
13  
14  
10  
11  
12  
13  
14  
R
R
R
R
R
OUT5  
OUT6  
OUT7  
OUT8  
OUT9  
AV  
CC  
AV  
AGND  
AGND  
DGND  
CC  
TCLK_R/F  
TCLK  
DGND  
DGND  
description  
The SN65LV1023A serializer and SN65LV1224A deserializer comprise a 10-bit serdes chipset designed to  
transmitandreceiveserialdataoverLVDSdifferentialbackplanesatequivalentparallelwordratesfrom10 MHz  
to 66 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 792-Mbps payload  
encoded throughput.  
Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC  
patterns, or the deserializer can be allowed to synchronize to random data. By using the synchronization mode,  
the deserializer establishes lock within specified, shorter time parameters.  
The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is  
available to place the output pins in the high-impedance state without losing PLL lock.  
The SN65LV1023A and SN65LV1224A are characterized for operation over ambient air temperature of 40°C  
to 85°C.  
ORDERING INFORMATION  
DEVICE  
Serializer  
PART NUMBER  
SN65LV1023ADB  
SN65LV1224ADB  
Deserializer  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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