SN54LVTH16374, SN74LVTH16374
3.3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS145P–MAY 1992–REVISED OCTOBER 2005
FEATURES
SN54LVTH16374 . . . WD PACKAGE
•
Members of the Texas Instruments Widebus™
Family
SN74LVTH16374 . . . DGG OR DL PACKAGE
(TOP VIEW)
•
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V Operation
and Low Static-Power Dissipation
1
1OE
1Q1
1Q2
GND
1Q3
1Q4
1CLK
1D1
48
47
2
3
46 1D2
•
•
•
•
•
•
•
•
•
Support Mixed-Mode Signal Operation (5-V
4
GND
1D3
1D4
45
44
43
42
Input and Output Voltages With 3.3-V VCC
)
5
Support Unregulated Battery Operation Down
to 2.7 V
6
7
V
CC
V
CC
Typical VOLP (Output Ground Bounce) <0.8 V
at VCC = 3.3 V, TA = 25°C
8
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
41 1D5
40 1D6
39 GND
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Ioff and Power-Up 3-State Support Hot
Insertion
1D7
1D8
2D1
38
37
36
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
35 2D2
34 GND
33 2D3
32 2D4
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
V
CC
V
CC
31
Latch-Up Performance Exceeds 500 mA Per
JESD 17
2Q5
2Q6
GND
2Q7
2Q8
2OE
30 2D5
29 2D6
28 GND
27 2D7
26 2D8
25 2CLK
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
DESCRIPTION/ORDERING INFORMATION
The 'LVTH16374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed for low-voltage
(3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These
devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working
registers.
These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock
(CLK), the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1992–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
On products compliant to MIL-PRF-38535, all parameters are
Instruments standard warranty. Production processing does not
tested unless otherwise noted. On all other products, production
necessarily include testing of all parameters.
processing does not necessarily include testing of all parameters.