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SN54LVTH16835WDR

更新时间： 2024-11-20 12:58:51
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德州仪器 - TI 输出元件驱动
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SN54LVTH16835WDR 数据手册

 浏览型号SN54LVTH16835WDR的Datasheet PDF文件第2页浏览型号SN54LVTH16835WDR的Datasheet PDF文件第3页浏览型号SN54LVTH16835WDR的Datasheet PDF文件第4页浏览型号SN54LVTH16835WDR的Datasheet PDF文件第5页浏览型号SN54LVTH16835WDR的Datasheet PDF文件第6页浏览型号SN54LVTH16835WDR的Datasheet PDF文件第7页 
SN54LVTH16835, SN74LVTH16835  
3.3-V ABT 18-BIT UNIVERSAL BUS DRIVERS  
WITH 3-STATE OUTPUTS  
SCBS713C – MARCH 1998 – REVISED APRIL 1999  
SN54LVTH16835 . . . WD PACKAGE  
SN74LVTH16835 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low Static-Power  
Dissipation  
NC  
NC  
Y1  
GND  
Y2  
Y3  
GND  
NC  
A1  
GND  
A2  
A3  
1
2
3
4
5
6
7
8
9
56  
55  
54  
53  
52  
51  
50  
49  
48  
Support Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
3.3-V V  
)
CC  
V
V
Support Unregulated Battery Operation  
Down to 2.7 V  
CC  
CC  
Y4  
Y5  
A4  
A5  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
Y6 10  
47 A6  
= 3.3 V, T = 25°C  
CC  
A
GND  
Y7  
GND  
A7  
11  
12  
46  
45  
I
and Power-Up 3-State Support Hot  
off  
Insertion  
Y8 13  
Y9 14  
44 A8  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
43 A9  
Y10 15  
Y11 16  
Y12 17  
GND 18  
42 A10  
41 A11  
40 A12  
39 GND  
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
Y13  
19  
38  
A13  
Flow-Through Architecture Optimizes PCB  
Layout  
Y14 20  
Y15 21  
37 A14  
36 A15  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
V
22  
35  
V
CC  
CC  
Y16 23  
Y17 24  
GND 25  
Y18 26  
OE 27  
LE 28  
34 A16  
33 A17  
32 GND  
31 A18  
30 CLK  
29 GND  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
Package Options Include Plastic Shrink  
Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
NC – No internal connection  
description  
The ’LVTH16835 devices are 18-bit universal bus drivers designed for low-voltage (3.3-V) V  
with the capability to provide a TTL interface to a 5-V system environment.  
operation, but  
CC  
Data flow from A to Y is controlled by the output-enable (OE) input. These devices operate in the transparent  
mode when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high  
or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of the clock.  
When OE is high, the outputs are in the high-impedance state.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
When V is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V  
through a pullup resistor;  
CC  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

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