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SN54LVTH16541

更新时间： 2024-11-23 23:03:07
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德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
7页 108K
描述
3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

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SN54LVTH16541 数据手册

 浏览型号SN54LVTH16541的Datasheet PDF文件第2页浏览型号SN54LVTH16541的Datasheet PDF文件第3页浏览型号SN54LVTH16541的Datasheet PDF文件第4页浏览型号SN54LVTH16541的Datasheet PDF文件第5页浏览型号SN54LVTH16541的Datasheet PDF文件第6页浏览型号SN54LVTH16541的Datasheet PDF文件第7页 
SN54LVTH16541, SN74LVTH16541  
3.3-V ABT 16-BIT BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SCBS691D – MAY 1997 – REVISED APRIL 1999  
SN54LVTH16541 . . . WD PACKAGE  
SN74LVTH16541 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low Static-Power  
Dissipation  
1OE1  
1Y1  
1Y2  
GND  
1Y3  
1Y4  
1OE2  
1A1  
1A2  
GND  
1A3  
1A4  
1
2
3
4
5
6
7
8
9
48  
47  
46  
45  
44  
43  
42  
41  
40  
Support Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
3.3-V V  
)
CC  
Support Unregulated Battery Operation  
Down to 2.7 V  
V
V
CC  
CC  
1Y5  
1Y6  
1A5  
1A6  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
GND 10  
39 GND  
= 3.3 V, T = 25°C  
CC  
A
1Y7  
1Y8  
1A7  
1A8  
11  
12  
38  
37  
I
and Power-Up 3-State Support Hot  
off  
Insertion  
2Y1 13  
2Y2 14  
GND 15  
2Y3 16  
2Y4 17  
36 2A1  
35 2A2  
34 GND  
33 2A3  
32 2A4  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
Distributed V  
and GND Pin Configuration  
CC  
Minimizes High-Speed Switching Noise  
V
18  
31  
V
CC  
CC  
Flow-Through Architecture Optimizes PCB  
Layout  
2Y5 19  
2Y6 20  
GND 21  
2Y7 22  
2Y8 23  
2OE1 24  
30 2A5  
29 2A6  
28 GND  
27 2A7  
26 2A8  
25 2OE2  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
Package Options Include Plastic Shrink  
Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
description  
These 16-bit buffers/drivers are designed specifically for low-voltage (3.3-V) V  
capability to provide a TTL interface to a 5-V system environment.  
operation, but with the  
CC  
These devices are noninverting 16-bit buffers composed of two 8-bit sections with separate output-enable  
signals. For either 8-bit buffer section, the two output-enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must  
be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 8-bit  
buffer section are in the high-impedance state.  
When V is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V  
through a pullup resistor;  
CC  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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