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SN54LVTH16952_07

更新时间： 2024-11-24 05:04:55
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德州仪器 - TI 输出元件
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15页 353K
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3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

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SN54LVTH16952_07 数据手册

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SN54LVTH16952, SN74LVTH16952  
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCBS697G – JULY 1997 – REVISED APRIL 2000  
SN54LVTH16952 . . . WD PACKAGE  
SN74LVTH16952 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low Static-Power  
Dissipation  
1OEAB  
1CLKAB  
1CLKENAB  
GND  
1OEBA  
1CLKBA  
1CLKENBA  
GND  
1
2
3
4
5
6
7
8
9
56  
55  
54  
53  
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V V  
)
1A1  
1A2  
52 1B1  
51 1B2  
CC  
Support Unregulated Battery Operation  
Down to 2.7 V  
V
50  
V
CC  
CC  
1A3  
1A4  
49 1B3  
48 1B4  
47 1B5  
46 GND  
45 1B6  
44 1B7  
43 1B8  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
A
1A5 10  
GND 11  
1A6 12  
1A7 13  
1A8 14  
I
and Power-Up 3-State Support Hot  
off  
Insertion  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
2B1  
2B2  
2B3  
GND  
2B4  
2B5  
2B6  
Distributed V  
High-Speed Switching Noise  
and GND Pins Minimize  
CC  
Flow-Through Architecture Optimizes PCB  
Layout  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
V
V
CC  
CC  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
2A7  
2A8  
GND  
2B7  
2B8  
GND  
2CLKENBA  
2CLKBA  
2OEBA  
Package Options Include Plastic Shrink  
Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
2CLKENAB  
2CLKAB  
2OEAB  
description  
The ’LVTH16952 devices are 16-bit registered transceivers designed for low-voltage (3.3-V) V operation, but  
CC  
with the capability to provide a TTL interface to a 5-V system environment.  
These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is stored  
intheregistersonthelow-to-hightransitionoftheclock(CLKABorCLKBA)input, providedthattheclock-enable  
(CLKENAB or CLKENBA) input is low. Taking the output-enable (OEAB or OEBA) input low accesses the data  
on either port.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
When V is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V  
through a pullup resistor;  
CC  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
Copyright 2000, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...15

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